Pixel circuit, display device, driving method of pixel circuit, and driving method of display device

ABSTRACT

A pixel circuit includes a drive transistor that has a gate connected to an input node and a source connected to an output node. The drive transistor supplies a driving current to an electrooptic element via the output node. A sampling transistor is connected between the input node and a signal line and samples an input signal from the signal line, which is retained in a retaining capacitance connected to the input node. The magnitude of the driving current is based on a value of the retained signal. The pixel circuit further includes a compensating circuit which detects a decrease in the driving current attendant on a secular change of the drive transistor from a side of the output node and feeds back a result of the detection to a side of the input node to compensate for the decrease.

CROSS REFERENCES TO RELATED APPLICATIONS

This is a Continuation application of the patent application Ser. No.13/618,974, filed Sep. 14, 2012, which is a Divisional application ofthe patent application Ser. No. 12/929,836, filed Feb. 18, 2011, nowU.S. Pat. No. 8,552,939, issued on Oct. 8, 2013, which is a Divisionalapplication of the patent application Ser. No. 11/171,416, filed Jul. 1,2005, now U.S. Pat. No. 7,893,895, issued Feb. 22, 2011, which claimspriority from Japanese Patent Application No.: 2004-198056, filed Jul.5, 2004, Japanese Patent Application No.: 2004-215056, filed Jul. 23,2004, Japanese Patent Application No.: 2004-201223, filed Jul. 8, 2004,and Japanese Patent Application No.: 2004-198057, filed Jul. 5, 2004,the entire contents of which being incorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to a pixel circuit that performs currentdriving of a load element disposed in each pixel. The present inventionalso relates to a display device having such pixel circuits arranged inthe form of a matrix, and particularly to a so-called active matrix typedisplay device that controls an amount of current passed through a loadelement such as an organic EL light emitting element or the like by aninsulated gate type electric field effect transistor provided withineach pixel circuit.

An image display device, for example, a liquid crystal display, has alarge number of liquid crystal pixels arranged in the form of a matrixand displays an image by controlling the intensity of transmitted orreflected incident light in each pixel according to image information tobe displayed. While this is true for an organic EL display using anorganic EL element in a pixel or the like, the organic EL element is aself light emission element unlike a liquid crystal pixel. Thus, theorganic EL display has advantages of, for example, higher imagevisibility, no need for a backlight, and higher response speed ascompared with a liquid crystal display. The brightness level (gradation)of each light emitting element can be controlled by the value of acurrent flowing through the light emitting element. The organic ELdisplay differs greatly from the liquid crystal display and the like inthat the organic EL display is of a so-called current control type.

As with the liquid crystal display, there is a simple matrix system andan active matrix system as the driving system of the organic EL display.The former system offers a simple structure but presents, for example, aproblem of difficulty in the realization of a large and high-definitiondisplay. Therefore, development in the active matrix system is now beingactively performed. This system controls a current flowing through alight emitting element within each pixel circuit by an active element(commonly a thin-film transistor (TFT)) provided within the pixelcircuit. The active matrix system is described in the followingdocuments.

[Patent Document 1]

-   Japanese Patent Laid-Open No. 2003-255856

[Patent Document 2]

-   Japanese Patent Laid-Open No. 2003-271095

Pixel circuits are disposed at respective parts where scanning lines, inthe form of rows, and signal lines, in the form of columns, intersecteach other in related art. Each pixel circuit includes at least athin-film type sampling transistor, a retaining capacitance, a thin-filmtype drive transistor, and a load element such as a light emittingelement or the like. The sampling transistor conducts between the sourceand the drain of the sampling transistor when the gate of the samplingtransistor is selected by a scanning line and samples a video signalfrom a signal line. The sampled signal is written to the retainingcapacitance and then retained by the retaining capacitance. The gate ofthe drive transistor is connected to the retaining capacitance, and oneof the source and the drain of the drive transistor is connected to theload element such as a light emitting element or the like. The gate ofthe drive transistor receives a source-reference gate voltage based onthe signal potential retained in the retaining capacitance. The drivetransistor passes a current between the source and the drain accordingto the gate voltage, and thus passes the current through the lightemitting element. The brightness of the light emitting element isgenerally proportional to the amount of current passed through the lightemitting element. Further, the amount of current passed by the drivetransistor is controlled by the gate voltage, that is, the signalpotential written to the retaining capacitance. The light emittingelement thus emits light at a brightness corresponding to the videosignal.

The operation characteristic of the drive transistor is expressed by thefollowing equation:

Ids=(½)μ(W/L)Cox(Vgs−Vth)²

In the transistor characteristic equation, Ids denotes a drain current.Vgs denotes a voltage applied to the gate with the source as areference. Vth denotes a threshold voltage of the transistor. Anothersymbol μ denotes the mobility of a semiconductor thin film forming achannel in the transistor. W denotes a channel width. L denotes achannel length. Cox denotes a gate capacitance. As is clear from thistransistor characteristic equation, when the thin-film transistoroperates in a saturation region and the gate voltage Vgs becomes higherthan the threshold voltage Vth, the thin-film transistor is brought intoan on state, and thus the drain current Ids flows. As is clear from theabove transistor characteristic equation, when the gate voltage Vgs isconstant, the same amount of drain current Ids should always flowthrough the light emitting element. However, there is a problem in thatdegradation in brightness occurs with the passage of time.

SUMMARY OF THE INVENTION

According to an embodiment of the present invention, there is provided apixel circuit disposed at a part where a scanning line and a signal lineintersect each other, the pixel circuit including at least: anelectrooptic element; a drive transistor; a sampling transistor; aretaining capacitance; the drive transistor having a gate connected toan input node, a source connected to an output node, and a drainconnected to a predetermined power supply potential; the electroopticelement having one terminal connected to the output node and anotherterminal connected to a predetermined potential; the sampling transistorbeing connected between the input node and the signal line; theretaining capacitance being connected to the input node; the samplingtransistor operating when selected by the scanning line, sampling aninput signal from the signal line, and retaining the input signal in theretaining capacitance; the drive transistor supplying a driving currentto the electrooptic element according to a signal potential retained inthe retaining capacitance; and a compensating circuit to compensate fora decrease in the driving current which decrease is attendant on asecular change of the drive transistor; the compensating circuitdetecting a decrease in the driving current from a side of the outputnode and feeding back a result of detection to a side of the input node.

Preferably, the compensating circuit detects a voltage drop occurring inthe electrooptic element, according to the driving current from the sideof the output node, obtains a difference by comparing a level of theinput signal with a level of the detected voltage drop, and adds apotential corresponding to the difference to the signal potentialretained in the retaining capacitance. Specifically, the compensatingcircuit includes: a detecting capacitance connected between the outputnode and a predetermined intermediate node; a switching transistorinserted between the intermediate node and the signal line; a switchingtransistor inserted between a terminal node connected to one terminal ofthe retaining capacitance and a predetermined ground potential; aswitching transistor inserted between the terminal node and the outputnode; and a switching transistor inserted between the terminal node andthe intermediate node.

The present invention also incorporates a display device includingscanning lines in a form of rows, signal lines in a form of columns, andpixel circuits arranged in a form of a matrix at parts where thescanning lines intersect the signal lines. Each pixel circuit includesat least an electrooptic element, a drive transistor, a samplingtransistor, and a retaining capacitance; the drive transistor has a gateconnected to an input node, a source connected to an output node, and adrain connected to a predetermined power supply potential; theelectrooptic element has one terminal connected to the output node andanother terminal connected to a predetermined potential; the samplingtransistor is connected between the input node and the signal line; theretaining capacitance is connected to the input node; the samplingtransistor operates when selected by the scanning line, samples an inputsignal from the signal line, and retains the input signal in theretaining capacitance; and the drive transistor supplies a drivingcurrent to the electrooptic element according to a signal potentialretained in the retaining capacitance, whereby display is made. As afeature, the pixel circuit further includes a compensating circuit forcompensating for a decrease in the driving current, which decrease isattendant on a secular change of the drive transistor. The compensatingcircuit detects a decrease in the driving current from a side of theoutput node and feeds back a result of detection to a side of the inputnode.

Preferably, the compensating circuit detects a voltage drop occurring inthe electrooptic element, according to the driving current from the sideof the output node, obtains a difference by comparing a level of theinput signal with a level of the detected voltage drop, and adds apotential corresponding to the difference of the signal potentialretained in the retaining capacitance. Specifically, the compensatingcircuit includes: a detecting capacitance connected between the outputnode and a predetermined intermediate node; a switching transistorinserted between the intermediate node and the signal line; a switchingtransistor inserted between a terminal node connected to one terminal ofthe retaining capacitance and a predetermined ground potential; aswitching transistor inserted between the terminal node and the outputnode; and a switching transistor inserted between the terminal node andthe intermediate node.

According to another embodiment of the present invention, there isprovided a driving method of a pixel circuit disposed at a part where ascanning line and a signal line intersect each other, the pixel circuitincluding at least an electrooptic element, a drive transistor, asampling transistor, and a retaining capacitance, the drive transistorhaving a gate connected to an input node, a source connected to anoutput node, and a drain connected to a predetermined power supplypotential, the electrooptic element having one terminal connected to theoutput node and another terminal connected to a predetermined potential,the sampling transistor being connected between the input node and thesignal line, the retaining capacitance being connected to the inputnode, the driving method including the steps of: the sampling transistoroperating when selected by the scanning line, sampling an input signalfrom the signal line, and retaining the input signal in the retainingcapacitance; the drive transistor supplying a driving current to theelectrooptic element according to a signal potential retained in theretaining capacitance and compensating for a decrease in the drivingcurrent which decrease is attendant on a secular change of the drivetransistor by detecting the decrease in the driving current from a sideof the output node and feeding back a result of detection to a side ofthe input node.

According to another embodiment of the present invention, there isprovided a driving method of a display device, the display deviceincluding scanning lines in a form of rows, signal lines in a form ofcolumns, and pixel circuits arranged in a form of a matrix at partswhere the scanning lines intersect the signal lines, the pixel circuitseach including at least an electrooptic element, a drive transistor, asampling transistor, and a retaining capacitance, the drive transistorhaving a gate connected to an input node, a source connected to anoutput node, and a drain connected to a predetermined power supplypotential, the electrooptic element having one terminal connected to theoutput node and another terminal connected to a predetermined potential,the sampling transistor being connected between the input node and thesignal line, the retaining capacitance being connected to the inputnode, the driving method including the steps of: when the samplingtransistor operates when selected by the scanning line, samples an inputsignal from the signal line, and retains the input signal in theretaining capacitance, and the drive transistor supplies a drivingcurrent to the electrooptic element according to a signal potentialretained in the retaining capacitance, whereby display is made,compensating for a decrease in the driving current which decrease isattendant on a secular change of the drive transistor by detecting thedecrease in the driving current from a side of the output node, andfeeding back a result of detection to a side of the input node.

According to another embodiment of the present invention, there isprovided a pixel circuit disposed at a part where a scanning line and asignal line intersect each other, the pixel circuit including at least:an electrooptic element; a drive transistor; a sampling transistor; aretaining capacitance; the drive transistor having a gate connected toan input node, a source connected to an output node, and a drainconnected to a predetermined power supply potential; the electroopticelement having one terminal connected to the output node and anotherterminal connected to a predetermined potential; the sampling transistorbeing connected between the input node and the signal line; theretaining capacitance being connected to the input node; the samplingtransistor operating when selected by the scanning line, sampling aninput signal from the signal line, and retaining the input signal in theretaining capacitance; the drive transistor supplying a driving currentto the electrooptic element according to a signal potential retained inthe retaining capacitance; and a compensating circuit for compensatingfor a decrease in the driving current which decrease is attendant on asecular change of the drive transistor; and in order to detect adecrease in the driving current from a side of the output node, and feedback a result of detection to a side of the input node; the compensatingcircuit, including detecting means for accumulating charge carried bythe driving current for a certain period of time and outputting adetection potential corresponding to an amount of charge accumulated,and feedback means for obtaining a difference by comparing a level ofthe input signal with a level of the detection potential and adding apotential corresponding to the difference to the signal potentialretained in the retaining capacitance.

Specifically, the compensating circuit includes: a switching transistorinserted between the output node and the electrooptic element; anotherswitching transistor connected to the output node; a detectingcapacitance connected between the switching transistor connected to theoutput node and a predetermined ground potential; a feedback capacitanceconnected between the output node and a predetermined intermediate node;a switching transistor inserted between the intermediate node and thesignal line; a switching transistor inserted between a terminal nodeconnected to one terminal of the retaining capacitance and thepredetermined ground potential; a switching transistor inserted betweenthe terminal node and the output node; and a switching transistorinserted between the terminal node and the intermediate node.

The present invention also incorporates a display device includingscanning lines in a form of rows, signal lines in a form of columns, andpixel circuits arranged in a form of a matrix at parts where thescanning lines intersect the signal lines. In the display device, eachpixel circuit includes at least an electrooptic element, a drivetransistor, a sampling transistor, and a retaining capacitance; thedrive transistor has a gate connected to an input node, a sourceconnected to an output node, and a drain connected to a predeterminedpower supply potential; the electrooptic element has one terminalconnected to the output node and another terminal connected to apredetermined potential; the sampling transistor is connected betweenthe input node and the signal line; the retaining capacitance isconnected to the input node; the sampling transistor operates whenselected by the scanning line, samples an input signal from the signalline, and retains the input signal in the retaining capacitance; thedrive transistor supplies a driving current to the electrooptic elementaccording to a signal potential retained in the retaining capacitancewhereby display is made; the pixel circuit further includes acompensating circuit for compensating for a decrease in the drivingcurrent which decrease is attendant on a secular change of the drivetransistor; and in order to detect a decrease in the driving currentfrom a side of the output node, and feed back a result of detection to aside of the input node, the compensating circuit includes detectingmeans for accumulating charge carried by the driving current for acertain period of time and outputting a detection potentialcorresponding to an amount of charge accumulated, and feedback means forobtaining a difference by comparing a level of the input signal with alevel of the detection potential and adding a potential corresponding tothe difference to the signal potential retained in the retainingcapacitance.

Specifically, the compensating circuit includes: a switching transistorinserted between the output node and the electrooptic element; anotherswitching transistor connected to the output node; a detectingcapacitance connected between the switching transistor connected to theoutput node and a predetermined ground potential; a feedback capacitanceconnected between the output node and a predetermined intermediate node;a switching transistor inserted between the intermediate node and thesignal line; a switching transistor inserted between a terminal nodeconnected to one terminal of the retaining capacitance and thepredetermined ground potential; a switching transistor inserted betweenthe terminal node and the output node; and a switching transistorinserted between the terminal node and the intermediate node.

According to another embodiment of the present invention, there isprovided a driving method of a pixel circuit disposed at a part where ascanning line and a signal line intersect each other, the pixel circuitincluding at least an electrooptic element, a drive transistor, asampling transistor, and a retaining capacitance, the drive transistorhaving a gate connected to an input node, a source connected to anoutput node, and a drain connected to a predetermined power supplypotential, the electrooptic element having one terminal connected to theoutput node and another terminal connected to a predetermined potential,the sampling transistor being connected between the input node and thesignal line, the retaining capacitance being connected to the inputnode, the driving method including the steps of: the sampling transistoroperating when selected by the scanning line, sampling an input signalfrom the signal line, and retaining the input signal in the retainingcapacitance; the drive transistor supplying a driving current to theelectrooptic element according to a signal potential retained in theretaining capacitance; in order to compensate for a decrease in thedriving current which decrease is attendant on a secular change of thedrive transistor by detecting the decrease in the driving current from aside of the output node and feeding back a result of detection to a sideof the input node, accumulating charge carried by the driving currentfor a certain period of time and obtaining a detection potentialcorresponding to an amount of charge accumulated; and obtaining adifference by comparing a level of the input signal with a level of thedetection potential and adding a potential corresponding to thedifference to the signal potential retained in the retainingcapacitance.

According to another embodiment of the present invention, there isprovided a driving method of a display device, the display deviceincluding scanning lines in a form of rows, signal lines in a form ofcolumns, and pixel circuits arranged in a form of a matrix at partswhere the scanning lines intersect the signal lines, the pixel circuitseach including at least an electrooptic element, a drive transistor, asampling transistor, and a retaining capacitance, the drive transistorhaving a gate connected to an input node, a source connected to anoutput node, and a drain connected to a predetermined power supplypotential, the electrooptic element having one terminal connected to theoutput node and another terminal connected to a predetermined potential,the sampling transistor being connected between the input node and thesignal line, the retaining capacitance being connected to the inputnode, the driving method including the steps of: when the samplingtransistor operates when selected by the scanning line, samples an inputsignal from the signal line, and retains the input signal in theretaining capacitance, and the drive transistor supplies a drivingcurrent to the electrooptic element according to a signal potentialretained in the retaining capacitance, whereby display is made, in orderto compensate for a decrease in the driving current which decrease isattendant on a secular change of the drive transistor by detecting thedecrease in the driving current from a side of the output node andfeeding back a result of detection to a side of the input node,accumulating charge carried by the driving current for a certain periodof time and obtaining a detection potential corresponding to an amountof charge accumulated; and obtaining a difference by comparing a levelof the input signal with a level of the detection potential and adding apotential corresponding to the difference to the signal potentialretained in the retaining capacitance.

According to another embodiment of the present invention, there isprovided a pixel circuit disposed at a part where a scanning line and asignal line intersect each other, the pixel circuit including at least:an electrooptic element; a drive transistor; a sampling transistor; aretaining capacitance; the drive transistor having a gate connected toan input node, a source connected to an output node, and a drainconnected to a predetermined power supply potential; the electroopticelement having one terminal connected to the output node and anotherterminal connected to a predetermined potential; the sampling transistorbeing connected between the input node and the signal line; theretaining capacitance being connected to the input node; the samplingtransistor operating when selected by the scanning line, sampling aninput signal from the signal line, and retaining the input signal in theretaining capacitance; the drive transistor supplying a driving currentto the electrooptic element according to a signal potential retained inthe retaining capacitance; and a compensating circuit for compensatingfor a decrease in the driving current which decrease is attendant on asecular change of the drive transistor. In order to detect a decrease inthe driving current from a side of the output node, and feed back aresult of detection to a side of the input node, the compensatingcircuit includes detecting means including a resistive componentinserted between the output node and a predetermined ground potentialand a capacitive component for retaining, as a detection potential, avoltage drop occurring in the resistive component according to thedriving current flowing from the output node to the ground potential,and feedback means for obtaining a difference by comparing a level ofthe input signal with a level of the detection potential, and adding apotential corresponding to the difference to the signal potentialretained in the retaining capacitance.

Specifically, the compensating circuit includes: a switching transistorinserted between the output node and the electrooptic element; anotherswitching transistor connected to the output node; a detectingtransistor diode-connected between the switching transistor connected tothe output node and the predetermined ground potential; a detectingcapacitance connected in parallel with the detecting transistor; afeedback capacitance connected between the output node and apredetermined intermediate node; a switching transistor inserted betweenthe intermediate node and the signal line; a switching transistorinserted between a terminal node connected to one terminal of theretaining capacitance and the predetermined ground potential; aswitching transistor inserted between the terminal node and the outputnode; and a switching transistor inserted between the terminal node andthe intermediate node.

The present invention also incorporates a display device includingscanning lines in a form of rows, signal lines in a form of columns, andpixel circuits arranged in a form of a matrix at parts where thescanning lines intersect the signal lines. In the display device, eachpixel circuit includes at least an electrooptic element, a drivetransistor, a sampling transistor, and a retaining capacitance; thedrive transistor has a gate connected to an input node, a sourceconnected to an output node, and a drain connected to a predeterminedpower supply potential; the electrooptic element has one terminalconnected to the output node and another terminal connected to apredetermined potential; the sampling transistor is connected betweenthe input node and the signal line; the retaining capacitance isconnected to the input node; the sampling transistor operates whenselected by the scanning line, samples an input signal from the signalline, and retains the input signal in the retaining capacitance; thedrive transistor supplies a driving current to the electrooptic elementaccording to a signal potential retained in the retaining capacitance,whereby display is made; the pixel circuit further includes acompensating circuit for compensating for a decrease in the drivingcurrent which decrease is attendant on a secular change of the drivetransistor. In order to detect a decrease in the driving current from aside of the output node, and feed back a result of detection to a sideof the input node, the compensating circuit includes detecting meansincluding a resistive component inserted between the output node and apredetermined ground potential and a capacitive component for retaining,as a detection potential, a voltage drop occurring in the resistivecomponent according to the driving current flowing from the output nodeto the ground potential, and feedback means for obtaining a differenceby comparing a level of the input signal with a level of the detectionpotential, and adding a potential corresponding to the difference to thesignal potential retained in the retaining capacitance.

Specifically, the compensating circuit includes: a switching transistorinserted between the output node and the electrooptic element; anotherswitching transistor connected to the output node; a detectingtransistor diode-connected between the switching transistor connected tothe output node and the predetermined ground potential; a detectingcapacitance connected in parallel with the detecting transistor; afeedback capacitance connected between the output node and apredetermined intermediate node; a switching transistor inserted betweenthe intermediate node and the signal line; a switching transistorinserted between a terminal node connected to one terminal of theretaining capacitance and the predetermined ground potential; aswitching transistor inserted between the terminal node and the outputnode; and a switching transistor inserted between the terminal node andthe intermediate node.

According to another embodiment of the present invention, there isprovided a driving method of a pixel circuit disposed at a part where ascanning line and a signal line intersect each other, the pixel circuitincluding at least an electrooptic element, a drive transistor, asampling transistor, and a retaining capacitance, the drive transistorhaving a gate connected to an input node, a source connected to anoutput node, and a drain connected to a predetermined power supplypotential, the electrooptic element having one terminal connected to theoutput node and another terminal connected to a predetermined potential,the sampling transistor being connected between the input node and thesignal line, the retaining capacitance being connected to the inputnode, the driving method including the steps of: the sampling transistoroperating when selected by the scanning line, sampling an input signalfrom the signal line, and retaining the input signal in the retainingcapacitance; and the drive transistor supplying a driving current to theelectrooptic element according to a signal potential retained in theretaining capacitance. In order to compensate for a decrease in thedriving current which decrease is attendant on a secular change of thedrive transistor by detecting the decrease in the driving current from aside of the output node and feeding back a result of detection to a sideof the input node, a voltage drop that occurs in a resistive componentinserted between the output node and a predetermined ground potentialaccording to the driving current flowing through the resistive componentis obtained, and the voltage drop is set as a detection potential, and adifference is obtained by comparing a level of the input signal with alevel of the detection potential, and a potential, corresponding to thedifference, is added to the signal potential retained in the retainingcapacitance.

According to another embodiment of the present invention, there isprovided a driving method of a display device, the display deviceincluding scanning lines in a form of rows, signal lines in a form ofcolumns, and pixel circuits arranged in a form of a matrix at partswhere the scanning lines intersect the signal lines, the pixel circuitseach including at least an electrooptic element, a drive transistor, asampling transistor, and a retaining capacitance, the drive transistorhaving a gate connected to an input node, a source connected to anoutput node, and a drain connected to a predetermined power supplypotential, the electrooptic element having one terminal connected to theoutput node and another terminal connected to a predetermined potential,the sampling transistor being connected between the input node and thesignal line, the retaining capacitance being connected to the inputnode, the driving method including the steps of: when the samplingtransistor operates when selected by the scanning line, samples an inputsignal from the signal line, and retains the input signal in theretaining capacitance, and the drive transistor supplies a drivingcurrent to the electrooptic element according to a signal potentialretained in the retaining capacitance, whereby display is made, in orderto compensate for a decrease in the driving current which decrease isattendant on a secular change of the drive transistor by detecting thedecrease in the driving current from a side of the output node andfeeding back a result of detection to a side of the input node,obtaining a voltage drop that occurs in a resistive component insertedbetween the output node and a predetermined ground potential accordingto the driving current flowing through the resistive component, andsetting the voltage drop as a detection potential; and obtaining adifference by comparing a level of the input signal with a level of thedetection potential, and adding a potential corresponding to thedifference to the signal potential retained in the retainingcapacitance.

According to another embodiment of the present invention, there isprovided a pixel circuit disposed at a part where a scanning line and asignal line intersect each other, the pixel circuit including at least:a light emitting element; a drive transistor; a sampling transistor; aretaining capacitance; the drive transistor having a gate connected toan input node, a source connected to an output node, and a drainconnected to a predetermined power supply potential; the light emittingelement having one terminal connected to the output node and anotherterminal connected to a predetermined potential; the sampling transistorbeing connected between the input node and the signal line; theretaining capacitance being connected to the input node; the samplingtransistor operating when selected by the scanning line, sampling aninput signal from the signal line, and retaining the input signal in theretaining capacitance; the drive transistor supplying a driving currentto the light emitting element according to a signal potential retainedin the retaining capacitance; the light emitting element emitting lightwith a voltage drop occurring according to the driving current; and acompensating circuit for compensating for a decrease in brightness dueto a secular change of the light emitting element; the compensatingcircuit detecting the voltage drop increasing according to the secularchange of the light emitting element from a side of the output node, andfeeding back a signal potential corresponding to a level of the detectedvoltage drop to a side of the input node; the drive transistor supplyinga sufficient driving current to compensate for the decrease inbrightness of the light emitting element according to the fed-backsignal potential.

Specifically, the compensating circuit includes two detectingcapacitances connected in series with each other between the output nodeand the input node; the two detecting capacitances connected in serieswith each other detect the voltage drop occurring in the light emittingelement from the side of the output node and each retain the voltagedrop according to a capacitance dividing ratio, and a level of an amountof the voltage drop, which amount is retained by the detectingcapacitance situated on the side of the input node, is fed back as thesignal potential. More specifically, the compensating circuit includes:a switching transistor inserted in parallel with one detectingcapacitance of the two detecting capacitances connected in series witheach other, the one detecting capacitance being situated on the side ofthe output node; a switching transistor inserted between the otherdetecting capacitance situated on the side of the input node and apredetermined ground potential; a switching transistor inserted betweenthe other detecting capacitance situated on the side of the input nodeand the input node; a switching transistor inserted between theretaining capacitance and the predetermined ground potential; and aswitching transistor inserted between the retaining capacitance and theoutput node.

According to another embodiment of the present invention, there isprovided an image display device including: scanning lines in a form ofrows; signal lines in a form of columns; and pixel circuits arranged ina form of a matrix at parts where the scanning lines intersect thesignal lines; the pixel circuits each including at least a lightemitting element, a drive transistor, a sampling transistor, and aretaining capacitance; the drive transistor having a gate connected toan input node, a source connected to an output node, and a drainconnected to a predetermined power supply potential; the light emittingelement having one terminal connected to the output node and anotherterminal connected to a predetermined potential; the sampling transistorbeing connected between the input node and the signal line; theretaining capacitance being connected to the input node; the samplingtransistor operating when selected by the scanning line, sampling aninput signal from the signal line, and retaining the input signal in theretaining capacitance; the drive transistor supplying a driving currentto the light emitting element according to a signal potential retainedin the retaining capacitance; the light emitting element emitting lightwith a voltage drop occurring according to the driving current; thepixel circuit further incorporating a compensating circuit forcompensating for a decrease in brightness due to a secular change of thelight emitting element; the compensating circuit detecting the voltagedrop increasing according to the secular change of the light emittingelement from a side of the output node, and feeding back a signalpotential corresponding to a level of the detected voltage drop to aside of the input node; the drive transistor supplying a sufficientdriving current to compensate for the decrease in brightness of thelight emitting element according to the fed-back signal potential.

Specifically, the compensating circuit includes two detectingcapacitances connected in series with each other between the output nodeand the input node; the two detecting capacitances, connected in serieswith each other, detect the voltage drop occurring in the light emittingelement from the side of the output node and each retain the voltagedrop according to a capacitance dividing ratio, and a level of an amountof the voltage drop, which amount is retained by the detectingcapacitance situated on the side of the input node, is fed back as thesignal potential. More specifically, the compensating circuit includes:a switching transistor inserted in parallel with one detectingcapacitance of the two detecting capacitances connected in series witheach other, the one detecting capacitance being situated on the side ofthe output node; a switching transistor inserted between the otherdetecting capacitance situated on the side of the input node and apredetermined ground potential; a switching transistor inserted betweenthe other detecting capacitance situated on the side of the input nodeand the input node; a switching transistor inserted between theretaining capacitance and the predetermined ground potential; and aswitching transistor inserted between the retaining capacitance and theoutput node.

According to another embodiment of the present invention, there isprovided a driving method of a pixel circuit disposed at a part where ascanning line and a signal line intersect each other, the pixel circuitincluding at least a light emitting element, a drive transistor, asampling transistor, and a retaining capacitance, the drive transistorhaving a gate connected to an input node, a source connected to anoutput node, and a drain connected to a predetermined power supplypotential, the light emitting element having one terminal connected tothe output node and another terminal connected to a predeterminedpotential, the sampling transistor being connected between the inputnode and the signal line, the retaining capacitance being connected tothe input node, the driving method including the steps of: the samplingtransistor operating when selected by the scanning line, sampling aninput signal from the signal line, and retaining the input signal in theretaining capacitance; the drive transistor supplying a driving currentto the light emitting element according to a signal potential retainedin the retaining capacitance; the light emitting element emitting lightwith a voltage drop occurring according to the driving current; in orderto compensate for a decrease in brightness due to a secular change ofthe light emitting element, detecting the voltage drop increasingaccording to the secular change of the light emitting element from aside of the output node, and feeding back a signal potentialcorresponding to a level of the detected voltage drop to a side of theinput node; and the drive transistor supplying a sufficient drivingcurrent to compensate for the decrease in brightness of the lightemitting element according to the fed-back signal potential.

According to a further embodiment of the present invention, there isprovided a driving method of a display device, the display deviceincluding scanning lines in a form of rows, signal lines in a form ofcolumns, and pixel circuits arranged in a form of a matrix at partswhere the scanning lines intersect the signal lines, the pixel circuitseach including at least a light emitting element, a drive transistor, asampling transistor, and a retaining capacitance, the drive transistorhaving a gate connected to an input node, a source connected to anoutput node, and a drain connected to a predetermined power supplypotential, the light emitting element having one terminal connected tothe output node and another terminal connected to a predeterminedpotential, the sampling transistor being connected between the inputnode and the signal line, the retaining capacitance being connected tothe input node, the driving method including the steps of: when thesampling transistor operates when selected by the scanning line, samplesan input signal from the signal line, and retains the input signal inthe retaining capacitance, the drive transistor supplies a drivingcurrent to the light emitting element according to a signal potentialretained in the retaining capacitance, and the light emitting elementemits light with a voltage drop occurring according to the drivingcurrent, whereby display is made, in order to compensate for a decreasein brightness due to a secular change of the light emitting element,detecting the voltage drop increasing according to the secular change ofthe light emitting element from a side of the output node, and feedingback a signal potential corresponding to a level of the detected voltagedrop to a side of the input node; and the drive transistor supplying asufficient driving current to compensate for the decrease in brightnessof the light emitting element according to the fed-back signalpotential.

A pixel circuit according to an embodiment of the present inventionincorporates a compensating circuit to compensate for a decrease indriving current with a secular change of a drive transistor. Thiscompensating circuit detects a decrease in the driving current from aside of an output node and feeds back a result of detection to a side ofan input node, whereby the decrease in the driving current is cancelledby circuit means. Therefore, even when the mobility of the drivetransistor is decreased and thereby the driving capability of the drivetransistor is decreased, feedback, to the side of the input node, isperformed so as to compensate for the decrease. Consequently, thedriving current can be maintained at the same constant level as aninitial level for a long period of time. It is thereby possible toprevent degradation in brightness which degradation is caused by thedrive transistor, and thus maintain screen uniformity over a long periodof time.

A pixel circuit according to another embodiment of the present inventionincorporates a compensating circuit to compensate for a decrease inbrightness due to a secular change of a light emitting element bycircuit means in a pixel unit. In addition, it is possible to compensatefor initial variations in brightness of light emitting elements whichvariations appear in pixels. This compensating circuit uses as aprinciple the fact that a voltage drop occurring in a light emittingelement increases according to a secular change of the light emittingelement. That is, when brightness is gradually decreased, due todegradation of the light emitting element with the passage of time, thevoltage drop tends to be conversely increased according to the decrease.This increasing voltage drop is detected from the side of an outputnode, and a signal potential corresponding to the detected voltage dropis fed back to the side of an input node. The drive transistor alwayssupplies a driving current from the output node in a direction tocompensate for decrease in brightness of the light emitting elementaccording to the fed-back signal potential. It is thereby possible toprevent degradation in brightness of the light emitting element, andthus maintain screen uniformity over a long period of time. In addition,it is possible to compensate for initial variations in brightness oflight emitting elements which variations appear in pixels, and therebyimprove screen uniformity.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a common configuration of an activematrix display device and a pixel circuit;

FIG. 2 is a circuit diagram showing a reference example of the pixelcircuit;

FIG. 3 is a timing chart of assistance in explaining the operation ofthe pixel circuit shown in FIG. 2;

FIG. 4 is a graph showing secular change of an I-V characteristic of anorganic EL element;

FIGS. 5A and 5B are graphs showing a secular change of an operatingpoint of a drive transistor and an organic EL element;

FIG. 6 is a circuit diagram showing another reference example of thepixel circuit;

FIG. 7 is a timing chart of assistance in explaining the operation ofthe pixel circuit shown in FIG. 6;

FIG. 8 is a circuit diagram showing an embodiment of a pixel circuitaccording to the present invention;

FIG. 9 is a timing chart of assistance in explaining the operation ofthe embodiment shown in FIG. 8;

FIG. 10 is a circuit diagram showing another embodiment of a pixelcircuit according to the present invention;

FIG. 11 is a timing chart of assistance in explaining the operation ofthe other embodiment shown in FIG. 10;

FIG. 12 is a circuit diagram showing another embodiment of a pixelcircuit according to the present invention;

FIG. 13 is a timing chart of assistance in explaining the operation ofthe other embodiment shown in FIG. 12;

FIG. 14 is a circuit diagram showing another embodiment of a pixelcircuit according to the present invention; and

FIG. 15 is a timing chart of assistance in explaining the operation ofthe other embodiment shown in FIG. 14.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will hereinafter bedescribed in detail with reference to the drawings. In order to explainthe background of the present invention, a common configuration of anactive matrix display device and a pixel circuit, included in the activematrix display device, will first be described as a reference examplewith reference to FIG. 1. As shown in the figure, the active matrixdisplay device includes a pixel array 1 as a main part and a peripheralcircuit group. The peripheral circuit group includes a horizontalselector 2, a drive scanner 3, a write scanner 4 and the like.

The pixel array 1 includes scanning lines WS in the form of rows, signallines DL in the form of columns, and pixel circuits 5 arranged in theform of a matrix at parts where the scanning lines WS intersect thesignal lines DL. The signal lines DL are driven by the horizontalselector 2. The scanning lines WS are scanned by the write scanner 4.Incidentally, other scanning lines DS are arranged in parallel with thescanning lines WS, and the scanning lines DS are scanned by the drivescanner 3. Each pixel circuit 5 samples a signal from the signal line DLwhen selected by the scanning line WS. Further, when selected by thescanning line DS, each pixel circuit 5 drives a load element accordingto the sampled signal. This load element is a light emitting element ofa current-driven type or the like formed in each pixel circuit 5.

FIG. 2 is a reference diagram showing a fundamental configuration of apixel circuit 5 shown in FIG. 1. The pixel circuit 5 includes, forexample, a thin-film transistor for sampling (sampling transistor Tr1),a thin-film transistor for drive (drive transistor Tr2), a thin-filmtransistor for switching (switching transistor Tr3), a retainingcapacitance C1, and a load element (organic EL light emitting element).

The sampling transistor Tr1 conducts when selected by a scanning line WSand samples a video signal from a signal line DL to retain the videosignal in the retaining capacitance C1. The drive transistor Tr2controls an amount of current applied to the light emitting element ELaccording to a signal potential retained in the retaining capacitanceC1. The switching transistor Tr3 is controlled by a scanning line DS,and turns on/off the application of the current to the light emittingelement EL. That is, the drive transistor Tr2 controls the lightemission luminance (brightness) of the light emitting element ELaccording to the amount of the applied current, whereas the switchingtransistor Tr3 controls the light emission time of the light emittingelement EL. Under these controls, the light emitting element EL includedin each pixel circuit 5 exhibits a brightness according to the videosignal so that the pixel array 1 shows a desired display.

FIG. 3 is a timing chart of assistance in explaining the operation ofthe pixel array 1 and the pixel circuit 5 shown in FIG. 2. During onehorizontal period (1H) at a start of one field period (1 f), a selectionpulse ws [1] is applied via the scanning line WS to the pixel circuit 5in a first row so that the sampling transistor Tr1 conducts. Thereby avideo signal is sampled from the signal line DL, and written to theretaining capacitance C1. One terminal of the retaining capacitance C1is connected to the gate of the drive transistor Tr2. Hence, when thevideo signal is written to the retaining capacitance C1, the gatepotential of the drive transistor Tr2 increases according to the writtensignal potential. At this time, a selection pulse ds [1] is applied tothe switching transistor Tr3 via the other scanning line DS. The lightemitting element EL continues emitting light while the selection pulseds [1] is applied. In the latter half of the field period 1 f, theselection pulse ds [1] is at a low level; therefore, the light emittingelement EL is in a non-emitting state. By adjusting the duty factor ofthe selection pulse ds [1], it is possible to adjust a ratio between alight emission period and a non-emission period, and thus obtain adesired screen brightness. On transition to a next horizontal period,signal pulses ws [2] and ds [2], for scanning, are applied fromrespective scanning lines WS and DS to pixel circuits in a second row.

FIG. 4 is a graph showing secular change of a current-voltage (I-V)characteristic of the organic EL element incorporated as a lightemitting element in the pixel circuit 5. In the graph, a curve shown asa solid line represents a characteristic at the time of an initialstate, and a curve shown as a broken line represents a characteristicafter a secular change. As shown in the graph, the I-V characteristic ofthe organic EL element is generally degraded with the passage of time.The drive transistor of the pixel circuit in the reference example shownin FIG. 2 is of a source follower configuration. The pixel circuitcannot cope with the secular change of the I-V characteristic of the ELelement, so light emission brightness is degraded.

FIG. 5A is a graph showing an operating point of the drive transistorTr2 and the light emitting element EL in an initial state. In thefigure, the axis of abscissas indicates drain-to-source voltage Vds ofthe drive transistor Tr2, and the axis of ordinates indicatesdrain-to-source current Ids of the drive transistor Tr2. As shown in thefigure, a source potential is determined by the operating point of thedrive transistor Tr2 and the light emitting element EL, and the voltagevalue has a different value depending on a gate voltage. Since the drivetransistor Tr2 operates in a saturation region, the drive transistor Tr2passes the driving current Ids having a current value defined by theabove-described transistor characteristic equation for Vgs correspondingto the source voltage at the operating point.

However, the I-V characteristic of the light emitting element EL isdegraded with the passage of time as shown in FIG. 4. As shown in FIG.5B, the operating point is changed because of this degradation with thepassage of time, and the source voltage of the transistor is changedeven when the same gate voltage is applied. Thereby the gate-to-sourcevoltage Vgs of the drive transistor Tr2 is changed, and the value of theflowing current is varied. At the same time, the value of currentflowing through the light emitting element EL is also changed. Thus, thepixel circuit of the source follower configuration in the referenceexample shown in FIG. 2 has a problem in that when the I-Vcharacteristic of the light emitting element EL is changed, thebrightness of the light emitting element EL is changed with the passageof time.

FIG. 6 shows another reference example of a pixel circuit. Thisreference example addresses the problem of the foregoing referenceexample shown in FIG. 2. In order to facilitate understanding, partscorresponding to those of the reference example of FIG. 2 are identifiedby corresponding reference numerals. An improvement is a change in theconnection of the switching transistor Tr3, whereby a bootstrap functionis realized. Specifically, the switching transistor Tr3 has a sourcegrounded, a drain connected to the source (S) of a drive transistor Tr2and one electrode of a retaining capacitance C1, and a gate connectedwith a scanning line DS. Incidentally, another electrode of theretaining capacitance C1 is connected to the gate (G) of the drivetransistor Tr2.

FIG. 7 is a timing chart of assistance in explaining the operation ofthe pixel circuit 5 shown in FIG. 6. During a first horizontal period 1Hof a field period 1 f, a selection pulse ws [1] is sent from a writescanner 4 to the pixel circuit 5 in a first row via a scanning line WS.Incidentally, a number in the brackets [ ] corresponds to a row numberof pixel circuits arranged in the form of a matrix. When the selectionpulse is applied, the sampling transistor Tr1 conducts. Thereby a inputsignal Vin is sampled from a signal line DL, and written to theretaining capacitance C1. At this time, a selection pulse ds [1] isapplied from a drive scanner 3 to the switching transistor Tr3 via thescanning line DS, and thus the switching transistor Tr3 is in an onstate. Hence one electrode of the retaining capacitance C1 and thesource (S) of the drive transistor Tr2 are at a GND level. Since theinput signal Vin is written to the retaining capacitance C1 with thisGND level as a reference, the gate potential (G) of the drive transistorTr2 is Vin.

Thereafter the selection pulse ws [1] for the sampling transistor Tr1 iscleared. Subsequently the selection pulse ds [1] for the switchingtransistor Tr3 is also cleared. Thereby the sampling transistor Tr1 andthe switching transistor Tr3 are turned off. Thus, the source (S) of thedrive transistor Tr2 is disconnected from a ground GND, and becomes anode connected to the anode of a light emitting element EL.

The gate of the drive transistor Tr2 receives the input signal Vinretained in the retaining capacitance C1. The drive transistor Tr2passes a drain current corresponding to the value of the input signalVin from a Vcc side to a GND side. As a result of the passing of thecurrent, the light emitting element EL emits light. At this time, avoltage drop occurs as a result of the passing of the current throughthe light emitting element EL, and a source potential (S)correspondingly increases from a GND side to a Vcc side. In the timingchart of FIG. 7, this increase is represented by

V. One terminal of the retaining capacitance C1 is connected to thesource (S) of the drive transistor Tr2, and the other terminal of theretaining capacitance C1 is connected to the high-impedance gate (G) ofthe drive transistor Tr2. Hence, when the source potential (S) increasesby

V, the gate potential (G) also rises by the amount of

V so that the net input signal Vin is maintained as it is. Thus, evenwhen the source potential (S) is varied by

V according to the current-voltage characteristic of the light emittingelement EL, the gate voltage Vgs=Vin holds at all times; therefore, thedrain current is kept constant. That is, even though the drivetransistor Tr2 is of a source follower configuration, the drivetransistor Tr2 functions as a constant-current source for the lightemitting element EL by the above-described bootstrap function.

When the selection pulse ds [1] is thereafter returned to a high level,the switching transistor Tr3 conducts to bypass the current to besupplied to the light emitting element EL. Therefore, the light emittingelement EL goes into a non-emitting state. When the field period if isthus ended, a next field period arrives in which a selection pulse ws[1] is applied to the sampling transistor Tr1 again to sample an inputvideo signal Vin*. Since levels of the video signals sampled in theprevious field period and this field period may differ from each other,a symbol * is added to the input video signal Vin to distinguish thesignals from each other. Incidentally, such video signal writing andlight emitting operations are performed on a line sequential basis (inrow units). Therefore, selection pulses ws [1], ws [2] . . . aresequentially applied to respective rows of pixels. Similarly, selectionpulse ds [1], ds [2] . . . are sequentially applied.

As described above, the pixel circuit of FIG. 6 can performconstant-current driving of the light emitting element EL even when thedrive transistor Tr2 is of an N-channel type, and thereby preventsdegradation in brightness due to secular change of the I-Vcharacteristic of the light emitting element EL. However, not only doessecular change due to aging occur in the light emitting element EL butalso secular change occurs in operation characteristics of a thin-filmtransistor having an amorphous silicon thin film as an element region.In the case of an N-channel type thin-film transistor, in particular,mobility μ tends to decrease with the passage of time. Thereby drivingcapability of the drive transistor Tr2 is decreased. Hence, even whenthe level of the input signal applied to the gate of the drivetransistor Tr2 is constant, the drain current supplied to the lightemitting element is reduced, and thus degradation in brightness mayoccur. Accordingly, the present invention improves the pixel circuitshown in FIG. 6 and incorporates a driving current compensatingfunction. Embodiments of a pixel circuit according to the presentinvention will hereinafter be described in detail. Incidentally, thepixel circuit can be incorporated as a pixel circuit in the displaydevice shown in FIG. 1.

FIG. 8 is a schematic circuit diagram showing an embodiment of a pixelcircuit according to the present invention. In order to facilitateunderstanding, corresponding reference numerals are used as much aspossible to denote parts corresponding to those of the pixel circuitaccording to the reference example shown in FIG. 6. As shown in thefigure, this pixel circuit 5 is disposed at a part where a scanning lineand a signal line intersect each other. A signal line DL is a singleline, while three scanning lines WS, X, and Y are bundled together andarranged in parallel with each other. The pixel circuit 5 includes anelectrooptic element EL, a drive transistor Tr2, a sampling transistorTr1, and a retaining capacitance C1 as fundamental components. The drivetransistor Tr2 is formed by an N-channel type thin-film transistor. Thedrive transistor Tr2 has a gate (G) connected to an input node A, asource (S) connected to an output node B, and a drain connected to apredetermined power supply potential Vcc. Incidentally, the gate voltageof the drive transistor Tr2 is denoted by Vgs, and the drain current ofthe drive transistor Tr2 is denoted by Ids. The electrooptic element ELis formed by a two-terminal light emitting element such as an organic ELelement or the like. The electrooptic element EL has an anode as oneterminal connected to the output node B, and a cathode as anotherterminal connected to a predetermined cathode potential Vcath. Thesampling transistor Tr1 is connected between the input node A and thesignal line DL. The gate of the sampling transistor Tr1 is connected tothe scanning line WS. The retaining capacitance C1 is connected to theinput node A.

In such a configuration, the sampling transistor Tr1 operates whenselected by the scanning line WS, samples an input signal Vsig from thesignal line DL, and retains the input signal Vsig in the retainingcapacitance C1. The drive transistor Tr2 supplies a driving current(drain current Ids) to the electrooptic element EL according to thesignal potential Vin retained in the retaining capacitance C1.

As a feature of the present invention, the pixel circuit 5 has acompensating circuit 7 for compensating for a decrease in the drivingcurrent (drain current Ids) which decrease is attendant on a secularchange of the drive transistor Tr2. This compensating circuit 7 detectsa decrease in the driving current (drain current Ids) from the side ofthe output node B, and feeds back a result of the detection to the sideof the input node A. Thus, even when the drain current Ids is decreasedwith the passage of time, feedback is performed so as to cancel thedecrease. Therefore, in spite of decrease in driving capability of thedrive transistor Tr2 with the passage of time, the drain current Idshaving the same level as an initial level can be ensured even after thepassage of a long period of time.

As for a concrete feedback configuration, the compensating circuit 7detects a voltage drop occurring in the electrooptic element ELaccording to the drain current Ids from the side of the output node B,obtains a difference by comparing the level of the input signal Vsigwith the level of the detected voltage drop, and adds a potentialcorresponding to the difference to the signal potential Vin retained inthe retaining capacitance C1. To supplement the above description, avoltage drop occurs when a driving current flows through the lightemitting element EL. This voltage drop is proportional to the magnitudeof the driving current. Hence, a change in the driving current can bedetected by monitoring the voltage drop. The detected voltage drop iscompared and evaluated with the input signal Vsig as a reference level.By feeding back a result of the comparison and evaluation to the side ofthe input node A, a decrease in the drain current Ids is cancelled.

As for a concrete configuration, the compensating circuit 7 includesfour N-channel type thin-film transistors and one capacitive elementadded to the pixel circuit of the reference example shown in FIG. 6.Specifically, the compensating circuit 7 includes: a detectingcapacitance C2 connected between the output node B and a predeterminedintermediate node C; a switching transistor Tr6 inserted between theintermediate node C and the signal line DL; a switching transistor Tr3inserted between a terminal node D connected to one terminal of theretaining capacitance C1 and a predetermined ground potential Vss; aswitching transistor Tr4 inserted between the terminal node D and theoutput node B; and a switching transistor Tr5 inserted between theterminal node D and the intermediate node C. Of these components, theswitching transistors Tr4, Tr5, and Tr6 are added transistor elements ascompared with the pixel circuit according to the reference example shownin FIG. 6.

The gate of the switching transistor Tr3 is connected to the scanningline WS. The gate of the switching transistor Tr4 is connected to thescanning line X. The gate of the switching transistor Tr5 is connectedto the scanning line Y. The gate of the switching transistor Tr6 isconnected to the scanning line X. As is clear from this, the samplingtransistor Tr1 and the switching transistor Tr3 are controlled to beturned on/off in the same timing via the common scanning line WS. Inaddition, the switching transistors Tr4 and Tr6 are controlled to beturned on/off in the same timing via the common scanning line X. Theremaining switching transistor Tr5 is controlled to be turned on/off indifferent timing from that of the other switching transistors via thescanning line Y.

The operation of the pixel circuit shown in FIG. 8 will be described indetail with reference to a timing chart of FIG. 9. The timing chart ofFIG. 9 shows one field (1 f) starting in timing T1 and ending in timingT6. The waveforms of a pulse ws applied to the scanning line WS, a pulsex applied to the scanning line X, and a pulse y applied to the scanningline Y are shown along a time axis T. In addition, changes in potentialsof the input node A, the intermediate node C, and the output node B areshown along the same time axis T. The change in the potential of theinput node A and the change in the potential of the output node B arerepresented by a solid line, and the change in the potential of theintermediate node C is represented by a dotted line to be distinguishedfrom the change in the potential of the input node A and the change inthe potential of the output node B.

In timing T0, before entering the field, the scanning lines WS and X aremaintained at a low level while the scanning line Y is at a high level.Therefore, the sampling transistor Tr1 and the switching transistorsTr3, Tr4, and Tr6 are off, and only the switching transistor Tr5 is inan on state. At this time, as shown in the timing chart, there is apotential difference substantially equal to an input potential Vinbetween the potential of the input node A and the potential of theoutput node B; therefore, the drive transistor Tr2 is in an on state tosupply a driving current (drain current) Ids to the light emittingelement EL.

When entering the field, the scanning line Y is changed to a low levelin timing T1. Thereby the switching transistor Tr5 is turned off. Theswitching transistors Tr3 and Tr4 are also in an off state in timing T1.Therefore, the terminal node D of the retaining capacitance C1 has ahigh impedance. However, since the potential of the input node Acontinues to be maintained, light emission is continued. The operationin timing T1 corresponds to a preparation for sampling an input signalin the field.

Nest, in timing T2, the input signal Vsig is actually sampled (signalwriting). Specifically, a selection pulse ws is applied to the scanningline WS, and a selection pulse x is applied to the scanning line X. As aresult, the scanning line WS and the scanning line X are both changed toa high level. Thereby the sampling transistor Tr1 is turned on, and theswitching transistor Tr3 is turned on. The switching transistors Tr4 andTr6 are also turned on. As a result, the terminal node D of theretaining capacitance C1 is pulled down to the ground potential Vss.Also, the output node B is sharply decreased to the ground level Vss. Atthe same time, a new input signal Vsig is sampled into the retainingcapacitance C1 from the signal line DL via the sampling transistor Tr1,changed to an on state. As a result, the signal potential Vin is writtento the retaining capacitance C1. In other words, the potential of theinput node A becomes Vin with respect to the output node B at the groundpotential Vss.

When one horizontal period (1H) assigned to the writing of the inputsignal has passed, the selection pulse ws is cleared in timing T3 toreturn the scanning line WS to a low level. Thereby the samplingtransistor Tr1 is turned off, and the switching transistor Tr3 is turnedoff. The terminal node D of the retaining capacitance C1 is, therefore,disconnected from the ground potential Vss. Instead, since the switchingtransistor Tr4 remains in an on state, the terminal node D of theretaining capacitance C1 is directly connected to the output node B. Thesignal potential Vin is thereby applied between the gate and the sourceof the drive transistor Tr2 (between the input node A and the outputnode B) so that a drain current Ids, corresponding to the signalpotential Vin, flows into the light emitting element EL. The lightemitting element EL thereby emits light tentatively.

When the drain current Ids flows through the light emitting element ELin timing T3, a voltage drop

Vel occurs, and the potential of the output node B increasescorrespondingly. At this time, bootstrap operation increases thepotential of the input node A by

Vel in such a manner as to be interlocked with the potential of theoutput node B.

The drain current Ids, flowing through the light emitting element EL,flows into the detecting capacitance C2 at the same time so that oneterminal of the detecting capacitance C2 obtains the potential

Vel. Another terminal of the detecting capacitance C2 is connected tothe signal line DL via the intermediate node C by the switchingtransistor Tr6 in an on state. The potential of the other terminal ofthe detecting capacitance C2 thereby becomes substantially Vin. Hence,the detecting capacitance C2 retains a difference

Vμ=Vin−

Vel between the potentials of the two terminals of the detectingcapacitance C2. In the timing chart of FIG. 9, this difference

Vμappears as a potential difference between the intermediate node C andthe output node B. When characteristics of the drive transistor Tr2 aredegraded with the passage of time and mobility μ of the drive transistorTr2 is decreased, the drain current Ids is correspondingly decreased. Asa result, the voltage drop

Vel occurring in the light emitting element EL is reduced. Thus, whenthe potential Vin serves as a reference, the value of the difference

Vμ is increased by an amount by which the voltage drop

Vel is reduced. That is, when the drain current Ids is decreased, due todegradation with the passage of time of the drive transistor, thedifference

Vμ is conversely increased. By feeding back the difference

Vμ to the side of the input node A, a decrease in the drain current Idsis cancelled so that the drain current Ids can be maintained at the sameconstant level as an initial level.

In timing T4, after the detection of the decrease in the drain currentIds, the scanning line X is changed from a high level to a low level.The switching transistors Tr4 and Tr6 are thereby turned off. That is,the terminal node D of the retaining capacitance C1 is disconnected fromthe output node B. Also, the intermediate node C connected to theterminal of the detecting capacitance C2 is disconnected from the signalline DL. A preparation for main emission operation is thereby completed.

Thereafter, in timing T5, the scanning line Y rises from a low level toa high level. The switching transistor Tr5 is thereby turned on toconnect the terminal node D directly with the intermediate node C.Hence, the retaining capacitance C1 and the detecting capacitance C2 areconnected in series with each other between the input node A and theoutput node B. The difference

Vμ retained by the detecting capacitance C2 as well as the signalpotential Vin, retained by the retaining capacitance C1, is appliedbetween the input node A and the output node B. The drive transistor Tr2supplies a drain current Ids corresponding to Vin+

Vμ to the light emitting element EL, whereby main emission is started.Due to a voltage drop occurring in the light emitting element EL, thepotential of the output node B is increased. The potential of the inputnode A is also increased in such a manner as to be interlocked with thepotential of the output node B. This bootstrap operation maintains apotential difference between the input node A and the output node B atthe value of Vin+

Vμ. As described above, when the drain current Ids is decreased, due todegradation of the drive transistor Tr2, the difference

Vμ is increased so as to compensate for the decrease. This feedbackoperation suppresses the variation in the drain current Ids so that thedrain current Ids, having the same level as an initial level, can bemade to flow irrespective of change in the mobility μ of the drivetransistor Tr2.

Thereafter, in timing T6, the scanning line Y falls to a low level,whereby the main light emission is ended. Thereby a series of operationsin the field is completed, and the next field is started.

FIG. 10 is a schematic circuit diagram showing another embodiment of apixel circuit according to the present invention. In order to facilitateunderstanding, corresponding reference numerals are used as much aspossible to denote parts corresponding to those of the pixel circuitaccording to the reference example shown in FIG. 6. As shown in thefigure, this pixel circuit 5 is disposed at a part where a scanning lineand a signal line intersect each other. A signal line DL is a singleline while three scanning lines WS, X, and Y are bundled together andarranged in parallel with each other. The pixel circuit 5 includes anelectrooptic element EL, a drive transistor Tr2, a sampling transistorTr1, and a retaining capacitance C1 as fundamental components. The drivetransistor Tr2 is formed by an N-channel type thin-film transistor. Thedrive transistor Tr2 has a gate (G) connected to an input node A, asource (S) connected to an output node B, and a drain connected to apredetermined power supply potential Vcc. Incidentally, the gate voltageof the drive transistor Tr2 is denoted by Vgs, and the drain current ofthe drive transistor Tr2 is denoted by Ids. The electrooptic element ELis formed by a two-terminal light emitting element such as an organic ELelement or the like. The electrooptic element EL has an anode as oneterminal connected to the side of the output node B, and a cathode asanother terminal connected to a predetermined cathode potential Vcath.The sampling transistor Tr1 is connected between the input node A andthe signal line DL. The gate of the sampling transistor Tr1 is connectedto the scanning line WS. The retaining capacitance C1 is connected tothe input node A.

In such a configuration, the sampling transistor Tr1 operates whenselected by the scanning line WS, samples an input signal Vsig from thesignal line DL, and retains the input signal Vsig in the retainingcapacitance C1. The drive transistor Tr2 supplies a driving current(drain current Ids) to the electrooptic element EL according to thesignal potential Vin retained in the retaining capacitance C1.

As a feature of the present invention, the pixel circuit 5 has acompensating circuit 7 for compensating for a decrease in the drivingcurrent (drain current Ids) which decrease is attendant on a secularchange of the drive transistor Tr2. This compensating circuit 7 detectsa decrease in the drain current Ids of the drive transistor Tr2 from theside of the output node B and feeds back a result of the detection tothe side of the input node A. For this purpose, the compensating circuit7 includes a detecting section, for accumulating charge carried by thedrain current Ids for a certain period of time and outputting adetection potential corresponding to an amount of charge accumulated,and a feedback section, for obtaining a difference

Vμ by comparing the level Vin of the input signal Vsig with the level ofthe detection potential and adding a potential corresponding to thedifference to the signal potential Vin retained in the retainingcapacitance C1.

Specifically, the compensating circuit 7 includes six transistors Tr3 toTr8 and two capacitances C2 and C3. The switching transistor Tr8 isinserted between the output node B and the electrooptic element EL. Theswitching transistor Tr7 is also connected to the output node B. Thedetecting capacitance C3 is connected between the switching transistorTr7 and a predetermined ground potential Vss. The switching transistorsTr7 and Tr8 and the detecting capacitance C3 form the above-describeddetecting section of the compensating circuit 7.

The feedback capacitance C2 is connected between the output node B and apredetermined intermediate node C. The switching transistor Tr6 isinserted between the intermediate node C and the signal line DL. Theswitching transistor Tr3 is inserted between a terminal node D connectedto one terminal of the retaining capacitance C1 and the predeterminedground potential Vss. The switching transistor Tr4 is inserted betweenthe terminal node D and the output node B. The switching transistor Tr5is inserted between the terminal node D and the intermediate node C. Thefeedback capacitance C2 and the switching transistors Tr5 and Tr6 formthe above-described feedback section of the compensating circuit 7.

The gate of the switching transistor Tr3 is connected to the scanningline WS. The gates of the switching transistors Tr4, Tr6, and Tr7 areconnected to another scanning line X. The switching transistors Tr5 andTr8 are connected to yet another scanning line Y.

The operation of the pixel circuit shown in FIG. 10 will be described indetail with reference to a timing chart of FIG. 11. The timing chart ofFIG. 11 shows one field (1 f) starting in timing T1 and ending in timingT6. The waveforms of a pulse ws applied to the scanning line WS, a pulsex applied to the scanning line X, and a pulse y applied to the scanningline Y are shown along a time axis T. In addition, changes in potentialsof the input node A, the intermediate node C, and the output node B areshown along the same time axis T. The change in the potential of theinput node A and the change in the potential of the output node B arerepresented by a solid line, and the change in the potential of theintermediate node C is represented by a dotted line to be distinguishedfrom the change in the potential of the input node A and the change inthe potential of the output node B.

In timing T0, before entering the field, the scanning lines WS and X aremaintained at a low level, while the scanning line Y is at a high level.Therefore, the sampling transistor Tr1 and the switching transistorsTr3, Tr4, Tr6, and Tr7 are off, and only the switching transistors Tr5and Tr8 are in an on state. At this time, as shown in the timing chart,there is a potential difference substantially equal to an inputpotential Vin between the potential of the input node A and thepotential of the output node B; therefore, the drive transistor Tr2 isin an on state to supply a driving current (drain current) Ids to thelight emitting element EL.

When entering the field, the scanning line Y is changed to a low levelin timing T1. Thereby the switching transistors Tr5 and Tr8 are turnedoff. Therefore, the light emitting element EL is disconnected from theoutput node B and thus goes into a non-emitting state. The switchingtransistors Tr3 and Tr4 are also in an off state in timing T1 inaddition to the switching transistor Tr5. Therefore, the terminal node Dof the retaining capacitance C1 has a high impedance. The operation intiming T1 corresponds to a preparation for sampling an input signal inthe field.

In timing T2, a selection pulse ws is applied to the scanning line WS,and a selection pulse x is applied to the scanning line X. The scanningline WS is thereby changed to a high level to turn on the samplingtransistor Tr1 and the switching transistor Tr3. At the same time, thescanning line X is changed from a low level to a high level so that thetransistors Tr4, Tr6, and Tr7 are turned on.

Since the switching transistor Tr3 is turned on, the terminal node D isconnected to the ground potential Vss. Since the switching transistorTr4 is turned on, the output node B is directly connected to theterminal node D. As a result, the potential of the output node B issharply decreased to the ground level Vss. At this time, since thesampling transistor Tr1 is also turned on, an input signal Vsig,supplied to the signal line DL, is written to the retaining capacitanceC1. The magnitude of a written signal potential Vin is substantiallyequal to that of the voltage of the input signal Vsig. Since theterminal node D is fixed at the ground potential Vss, the potential ofthe input node A is precisely Vin as shown in the timing chart. Thisinput potential Vin is applied between the gate G and the source S ofthe drive transistor Tr2 so that a drain current Ids, corresponding tothe signal potential Vin, flows out from the output node B.

However, since the switching transistor Tr8 is in an off state asdescribed above, the drain current Ids is not supplied to the lightemitting element EL. The light emitting element EL, therefore, continuesmaintaining the non-emitting state.

When one horizontal period (1H), assigned to the operation of writing ofthe input signal, has passed, the selection pulse ws is cleared intiming T3 to return the scanning line WS from a high level to a lowlevel. Thereby the sampling transistor Tr1 and the switching transistorTr3 are turned off. As a result, the terminal node D and the output nodeB are disconnected from the ground potential Vss. In response to this,the potential of the output node B starts to rise, and the drain currentIds starts to flow into the detecting capacitance C3 via the switchingtransistor Tr7 in an on state. With accumulation of charge, thepotential of the output node B continues rising. At this time, since theterminal node D is disconnected from the ground potential Vss, thepotential of the input node A rises in such a manner as to beinterlocked with the potential of the output node B. A potentialdifference Vin between the input node A and the output node B is keptconstant.

In timing T4, after the passage of a predetermined time t from timingT3, the selection pulse x is cleared to return the scanning line X froma high level to a low level. The transistors Tr4, Tr7 and Tr6 arethereby turned off. In a stage in which the switching transistor Tr7 isturned off, the charge accumulation of the detecting capacitance C3 iscompleted. The potential of the detecting capacitance C3, whichpotential corresponds to the accumulated charge, is given by

VC3=(Ids/C3)·t. As is clear from this equation, the detection potential

VC3 is proportional to the drain current Ids because the capacitancevalue C3 and the accumulation time t are fixed. That is, the detectionpotential

VC3 has a value proportional to the drain current Ids of the drivetransistor Tr2. As the mobility μ of the drive transistor Tr2 isdecreased with the passage of time, the detection potential

VC3 is correspondingly lowered.

The switching transistors Tr6 and Tr7 are in an on state untilimmediately before the scanning line X falls to a low level in timingT4. The feedback capacitance C2 is, therefore, at the potential Vin ofthe input signal Vsig on the side of the intermediate node C. Thepotential of the feedback capacitance C2 on the side of the output nodeB is precisely

VC3. Hence, when the selection pulse x is cleared and the switchingtransistors Tr6 and Tr7 are thereby turned off, the feedback capacitanceC2 holds a potential

Vμ corresponding to a difference between the potential Vin and thedetection potential

VC3. That is, the potential

Vμ is expressed by

Vμ=Vin−

VC3. As described above, when the drain current Ids is decreased, due todegradation of the drive transistor Tr2, the detection potential

VC3 is also decreased. Hence, the potential

Vμ is increased. By feeding back the potential

Vμ held by the feedback capacitance C2 to the side of the input node A,it is possible to cancel the decrease in the drain current Ids. Thisfeedback operation makes it possible to continue supplying the draincurrent Ids having the same level as an initial level even when adegradation occurs in an operation characteristic of the drivetransistor Tr2 such as mobility or the like.

The present invention compares and determines the magnitude of thedetection potential

VC3 with the signal potential Vin of the input signal Vsig as areference. The signal potential Vin varies in a predetermined range (forexample 0 to 5 V). The drain current Ids correspondingly varies, and thedetection potential

VC3 has a corresponding level. The signal potential Vin and thedetection potential

VC3 thus change in the same direction so that dynamic comparison ispossible. As a precondition, the dynamic range of the signal potentialVin and the dynamic range of the detection potential

VC3 need to substantially match each other. Supposing that the dynamicrange of the signal potential Vin is 0 to 5 V as described above, it isdesirable that the detection potential

VC3 vary in substantially a range of 0 to 5 V. In order to set thedynamic range of the detection potential

VC3 to the desired range, it is necessary to set the accumulation time tand the capacitance of the detecting capacitance C3 appropriately.

Thereafter, in timing T5, a selection pulse y is applied to change thescanning line Y from a low level to a high level. The switchingtransistors Tr5 and Tr8 are thereby turned on. By turning on theswitching transistor Tr8, the anode of the electrooptic element EL isdirectly connected to the output node B. By turning on the switchingtransistor Tr5, the intermediate node C is directly connected to theterminal node D. The potential

Vμ, retained by the feedback capacitance C2, as well as the signalpotential Vin, retained by the retaining capacitance C1, are appliedbetween the input node A and the output node B. The drive transistor Tr2supplies a drain current Ids corresponding to Vin+

Vμ to the light emitting element EL, whereby light emission is started.Due to a voltage drop occurring in the light emitting element EL, thepotential of the output node B is increased. The potential of the inputnode A is also increased in such a manner as to be interlocked with thepotential of the output node B. This bootstrap operation maintains apotential difference between the input node A and the output node B atthe value of Vin+

Vμ. As described above, when the drain current Ids is decreased, due todegradation of the drive transistor Tr2, the potential

Vμ is increased so as to compensate for the decrease. This feedbackoperation suppresses the variation in the drain current Ids so that thedrain current Ids, having the same level as an initial level, can bemade to flow irrespective of change in the mobility μ of the drivetransistor Tr2.

Thereafter, in timing T6, the scanning line Y falls to a low level toturn off the switching transistor Tr8 whereby the light emission isended. Thereby a series of operations in the field is completed, and thenext field is started.

FIG. 12 is a schematic circuit diagram showing another embodiment of apixel circuit according to the present invention. In order to facilitateunderstanding, corresponding reference numerals are used as much aspossible to denote parts corresponding to those of the pixel circuitaccording to the reference example shown in FIG. 6. As shown in thefigure, this pixel circuit 5 is disposed at a part where a scanning lineand a signal line intersect each other. A signal line DL is a singleline, while three scanning lines WS, X, and Y are bundled together andarranged in parallel with each other. The pixel circuit 5 includes anelectrooptic element EL, a drive transistor Tr2, a sampling transistorTr1, and a retaining capacitance C1 as fundamental components. The drivetransistor Tr2 is formed by an N-channel type thin-film transistor. Thedrive transistor Tr2 has a gate (G) connected to an input node A, asource (S) connected to an output node B, and a drain connected to apredetermined power supply potential Vcc. Incidentally, the gate voltageof the drive transistor Tr2 is denoted by Vgs, and the drain current ofthe drive transistor Tr2 is denoted by Ids. The electrooptic element ELis formed by a two-terminal light emitting element such as an organic ELelement or the like. The electrooptic element EL has an anode, as oneterminal connected to the side of the output node B, and a cathode, asanother terminal connected to a predetermined cathode potential Vcath.The sampling transistor Tr1 is connected between the input node A andthe signal line DL. The gate of the sampling transistor Tr1 is connectedto the scanning line WS. The retaining capacitance C1 is connected tothe input node A.

In such a configuration, the sampling transistor Tr1 operates whenselected by the scanning line WS, samples an input signal Vsig from thesignal line DL, and retains the input signal Vsig in the retainingcapacitance C1. The drive transistor Tr2 supplies a driving current(drain current Ids) to the electrooptic element EL according to thesignal potential Vin retained in the retaining capacitance C1.

As a feature of the present invention, the pixel circuit 5 has acompensating circuit 7 for compensating for a decrease in the drivingcurrent (drain current Ids), which decrease is attendant on a secularchange of the drive transistor Tr2. In order to detect a decrease in thedrain current Ids of the drive transistor Tr2, from the side of theoutput node B, and feed back a result of the detection to the side ofthe input node A, the compensating circuit 7 includes a detectingsection and feedback section. The a detecting section includes aresistive component, inserted between the output node B and apredetermined ground potential Vss, and a capacitive component forretaining, as a detection potential, a voltage drop occurring in theresistive component according to the drain current Ids flowing from theoutput node B to the ground potential Vss. The feedback section obtainsa difference

Vμ by comparing the level Vin of the input signal Vsig with the level ofthe detection potential and adds a potential corresponding to thedifference to the signal potential Vin retained in the retainingcapacitance C1.

Specifically, the compensating circuit 7, shown in FIG. 12, includes twocapacitive elements C2 and C3 and seven transistors Tr3 to Tr9. Theswitching transistor Tr8 is inserted between the output node B and theanode of the electrooptic element EL. The switching transistor Tr7 isalso connected to the output node B. The transistor Tr9 isdiode-connected between the switching transistor Tr7 and thepredetermined ground potential Vss. The transistor Tr9 functions as adetecting transistor. The capacitive element C3 is connected in parallelwith the detecting transistor Tr9. The capacitive element C3 functionsas a detecting capacitance. The diode-connected detecting transistor Tr9corresponds to the resistive component provided in the detecting sectionof the compensating circuit 7. The detecting capacitance C3 correspondsto the capacitive component provided in the detecting section of thecompensating circuit 7.

The other capacitive element C2 is connected between the output node Band a predetermined intermediate node C. The capacitive element C2 formsa feedback capacitance. The switching transistor Tr6 is inserted betweenthe intermediate node C and the signal line DL. The switching transistorTr3 is inserted between a terminal node D connected to one terminal ofthe retaining capacitance C1 and the predetermined ground potential Vss.The switching transistor Tr4 is inserted between the terminal node D andthe output node B. The switching transistor Tr5 is inserted between theterminal node D and the intermediate node C.

As with the sampling transistor Tr1, the gate of the switchingtransistor Tr3 is connected to the scanning line WS. The gates of theswitching transistors Tr4, Tr6, and Tr7 are each connected to thescanning line X. The gates of the switching transistors Tr5 and Tr8 areconnected to the scanning line Y.

The operation of the pixel circuit shown in FIG. 12 will be described indetail with reference to a timing chart of FIG. 13. The timing chart ofFIG. 13 shows one field (1 f) starting in timing T1 and ending in timingT6. The waveforms of a pulse ws applied to the scanning line WS, a pulsex applied to the scanning line X, and a pulse y applied to the scanningline Y are shown along a time axis T. In addition, changes in potentialsof the input node A, the intermediate node C, and the output node B areshown along the same time axis T. The change in the potential of theinput node A and the change in the potential of the output node B arerepresented by a solid line, and the change in the potential of theintermediate node C is represented by a dotted line to be distinguishedfrom the change in the potential of the input node A and the change inthe potential of the output node B.

In timing T0, before entering the field, the scanning lines WS and X aremaintained at a low level while the scanning line Y is at a high level.Therefore, the sampling transistor Tr1 and the switching transistorsTr3, Tr4, Tr6, and Tr7 are off, and only the switching transistors Tr5and Tr8 are in an on state. At this time, as shown in the timing chart,there is a potential difference substantially equal to an inputpotential Vin between the potential of the input node A and thepotential of the output node B, and, therefore, the drive transistor Tr2is in an on state to supply a driving current (drain current) Ids to thelight emitting element EL.

When entering the field, the scanning line Y is changed to a low levelin timing T1. Thereby the switching transistors Tr5 and Tr8 are turnedoff. Therefore, the light emitting element EL is disconnected from theoutput node B and thus goes into a non-emitting state. The switchingtransistors Tr3 and Tr4 are also in an off state in timing T1 inaddition to the switching transistor Tr5. Therefore, the terminal node Dof the retaining capacitance C1 has a high impedance. The operation intiming T1 corresponds to a preparation for sampling an input signal inthe field.

In timing T2, a selection pulse ws is applied to the scanning line WS,and a selection pulse x is applied to the scanning line X. The scanningline WS is thereby changed to a high level to turn on the samplingtransistor Tr1 and the switching transistor Tr3. At the same time, thescanning line X is changed from a low level to a high level so that thetransistors Tr4, Tr6, and Tr7 are turned on.

Since the switching transistor Tr3 is turned on, the terminal node D isconnected to the ground potential Vss. Since the switching transistorTr4 is turned on, the output node B is directly connected to theterminal node D. As a result, the potential of the output node B issharply decreased to the ground potential Vss. At this time, since thesampling transistor Tr1 is also turned on, an input signal Vsig suppliedto the signal line DL is written to the retaining capacitance C1. Themagnitude of a written signal potential Vin is substantially equal tothat of the voltage of the input signal Vsig. Since the terminal node Dis fixed at the ground potential Vss, the potential of the input node Ais precisely Vin as shown in the timing chart. This input potential Vinis applied between the gate G and the source S of the drive transistorTr2 so that a drain current Ids corresponding to the signal potentialVin flows out from the output node B.

However, since the switching transistor Tr8 is in an off state asdescribed above, the drain current Ids is not supplied to the lightemitting element EL. The light emitting element EL, therefore, continuesmaintaining the non-emitting state.

When one horizontal period (1H), assigned to the operation of writing ofthe input signal, has passed, the selection pulse ws is cleared intiming T3 to change the scanning line WS to a low level. Thereby theN-channel type sampling transistor Tr1 is turned off, and the switchingtransistor Tr3 is also turned off. As a result, the input node A isdisconnected from the signal line DL, and thus brought into ahigh-impedance state. Also, the terminal node D and the output node Bare disconnected from the ground potential Vss in a state of beingconnected to each other. In response to this, the drive transistor Tr2starts to supply the drain current Ids according to the signal potentialVin applied between the gate G and the source S of the drive transistorTr2. Therefore, the potential of the output node B rises. The potentialof the input node A rises by precisely the amount Vin in such a manneras to be interlocked with the potential of the output node B. At thistime, since the switching transistor Tr8 remains in an off state, thedrain current Ids does not flow through the electrooptic element EL, andthus the electrooptic element EL remains in the non-emitting state.Since the switching transistor Tr7 is in an on state, however, the draincurrent Ids flows from the output node B to the ground potential Vss viathe switching transistors Tr7 and Tr9. When the drain current Ids flowsthrough the detecting transistor, formed by the diode-connectedtransistor Tr9, a voltage drop

VTr9 occurs according to the magnitude of the drain current Ids. Thisvoltage drop

VTr9 is sampled as a detection potential across the capacitance C3.Since the output node B is connected to the detecting capacitance C3with the switching transistor Tr7 turned on, the potential of the outputnode B is at the level

VTr9 as shown in the timing chart.

Meanwhile, since the switching transistor Tr6 is also in an on state,the intermediate node C is connected to the signal line DL. As a result,the intermediate node C, situated on the left side of the feedbackcapacitance C2, is at the signal potential Vin of the input signal Vsig.On the other hand, the output node B on the right side of the feedbackcapacitance C2 is at the potential

VTr9, as described above. Hence, a potential difference

Vμ=Vin−

VTr9 occurs across the feedback capacitance C2. The feedback capacitanceC2 thus obtains the difference

Vμ by comparing the level Vin of the input signal Vsig with the level ofthe above-described detection potential

VTr9. The detection potential

VTr9 represents the voltage drop according to the drain current Ids.Therefore, when the mobility or the like of the drive transistor Tr2 isdecreased, due to degradation of the drive transistor Tr2 with thepassage of time and thus the drain current Ids is reduced, the detectionpotential

VTr9 is also decreased. When the detection potential

VTr9 is decreased, the difference

Vμ is conversely increased. By feeding back the difference

Vμ to the side of the input node A, the reduction in the drain currentIds can be cancelled. Even when a degradation of the drive transistorTr2 with the passage of time lowers the capability of supplying thedrain current Ids, the driving current having the same level as that ofan initial drain current can be ensured by this feedback operation.

Thereafter, in timing T4, the selection pulse x is cleared to change thescanning line X to a low level. The switching transistors Tr4, Tr6 andTr7 are thereby turned off. The feedback capacitance C2 is disconnectedfrom the signal line DL and the ground potential Vss and retains theabove-described difference

Vμ.

Thereafter, in timing T5, a selection pulse y is applied to change thescanning line Y from a low level to a high level. The switchingtransistors Tr5 and Tr8 are thereby turned on. By turning on theswitching transistor Tr8, the anode of the electrooptic element EL isdirectly connected to the output node B. By turning on the switchingtransistor Tr5, the intermediate node C is directly connected to theterminal node D. The difference

Vμretained by the C2 as well as the signal potential Vin retained by theC1 is applied between the input node A and the output node B. The drivetransistor Tr2 supplies a drain current Ids corresponding to Vin+

Vμ to the light emitting element EL whereby light emission is started.Due to a voltage drop occurring in the light emitting element EL, thepotential of the output node B is increased. The potential of the inputnode A is also increased in such a manner as to be interlocked with thepotential of the output node B. This bootstrap operation maintains apotential difference between the input node A and the output node B atthe value of Vin+

Vμ. As described above, when the drain current Ids is decreased, due todegradation of the drive transistor Tr2, the difference

Vμ is increased so as to compensate for the decrease. This feedbackoperation suppresses the variation in the drain current Ids so that thedrain current Ids, having the same level as an initial level, can bemade to flow irrespective of change in the mobility μ of the drivetransistor Tr2.

Thereafter, in timing T6, the scanning line Y falls to a low level toturn off the switching transistor Tr8, whereby the light emission isended. Thereby a series of operations in the field is completed, and anext field is started.

Thus, the compensating circuit, according to the present embodiment ofthe present invention, employs a detecting section including a resistivecomponent, inserted between the output node and the ground potential,and a capacitive component, for retaining, as a detection potential, avoltage drop occurring in the resistive component according to thedriving current flowing from the output node to the ground potential.Since the voltage drop occurring in the resistive component is detected,the detection itself takes only a short time, and there is a sufficienttiming margin. On the other hand, it is possible to employ a detectingsection for accumulating charge carried by the driving current for acertain period of time and outputting a detection potentialcorresponding to an amount of charge accumulated. However, a systemusing a detection potential corresponding to an amount of chargeaccumulated requires a predetermined time for charge accumulation, andmay, therefore, squeeze a timing margin in the entire sequence. Forcomparison, the system using a detection potential corresponding to anamount of charge accumulated will be described in the following withreference to FIGS. 10 and 11.

FIG. 10 is a schematic circuit diagram showing an embodiment of a pixelcircuit according to a comparison example. In order to facilitateunderstanding, corresponding reference numerals are used as much aspossible to denote parts corresponding to those of the pixel circuitaccording to the embodiment of the present invention shown in FIG. 12.As shown in the figure, this pixel circuit 5 is disposed at a part wherea scanning line and a signal line intersect each other. A signal line DLis a single line, while three scanning lines WS, X, and Y are bundledtogether and arranged in parallel with each other. The pixel circuit 5includes an electrooptic element EL, a drive transistor Tr2, a samplingtransistor Tr1, and a retaining capacitance C1 as fundamentalcomponents. The drive transistor Tr2 is formed by an N-channel typethin-film transistor. The drive transistor Tr2 has a gate (G) connectedto an input node A, a source (S) connected to an output node B, and adrain connected to a predetermined power supply potential Vcc.Incidentally, the gate voltage of the drive transistor Tr2 is denoted byVgs, and the drain current of the drive transistor Tr2 is denoted byIds. The electrooptic element EL is formed by a two-terminal lightemitting element such as an organic EL element or the like. Theelectrooptic element EL has an anode as one terminal connected to theside of the output node B, and a cathode as another terminal connectedto a predetermined cathode potential Vcath. The sampling transistor Tr1is connected between the input node A and the signal line DL. The gateof the sampling transistor Tr1 is connected to the scanning line WS. Theretaining capacitance C1 is connected to the input node A.

In such a configuration, the sampling transistor Tr1 operates whenselected by the scanning line WS, samples an input signal Vsig from thesignal line DL, and retains the input signal Vsig in the retainingcapacitance C1. The drive transistor Tr2 supplies a driving current(drain current Ids) to the electrooptic element EL according to thesignal potential Vin retained in the retaining capacitance C1.

As a feature of the comparison example, the pixel circuit 5 has acompensating circuit 7 for compensating for a decrease in the drivingcurrent (drain current Ids) which decrease is attendant on a secularchange of the drive transistor Tr2. This compensating circuit 7 detectsa decrease in the driving current (drain current Ids) of the drivetransistor Tr2, from the side of the output node B, and feeds back aresult of the detection to the side of the input node A. For thispurpose, the compensating circuit 7 includes a detecting section, foraccumulating charge carried by the drain current Ids for a certainperiod of time and outputting a detection potential corresponding to anamount of charge accumulated, and a feedback section, for obtaining adifference

Vμ by comparing the level Vin of the input signal Vsig with the level ofthe detection potential and adding a potential corresponding to thedifference to the signal potential Vin retained in the retainingcapacitance C1.

Specifically, the compensating circuit 7 includes six transistors Tr3 toTr8 and two capacitances C2 and C3. The switching transistor Tr8 isinserted between the output node B and the electrooptic element EL. Theswitching transistor Tr7 is also connected to the output node B. Thedetecting capacitance C3 is connected between the switching transistorTr7 and a predetermined ground potential Vss. The switching transistorsTr7 and Tr8 and the detecting capacitance C3 form the above-describeddetecting section of the compensating circuit 7.

The feedback capacitance C2 is connected between the output node B and apredetermined intermediate node C. The switching transistor Tr6 isinserted between the intermediate node C and the signal line DL. Theswitching transistor Tr3 is inserted between a terminal node D connectedto one terminal of the retaining capacitance C1 and the predeterminedground potential Vss. The switching transistor Tr4 is inserted betweenthe terminal node D and the output node B. The switching transistor Tr5is inserted between the terminal node D and the intermediate node C. Thefeedback capacitance C2 and the switching transistors Tr5 and Tr6 formthe above-described feedback section of the compensating circuit 7.

The gate of the switching transistor Tr3 is connected to the scanningline WS. The gates of the switching transistors Tr4, Tr6, and Tr7 areconnected to another scanning line X. The switching transistors Tr5 andTr8 are connected to yet another scanning line Y.

The operation of the pixel circuit shown in FIG. 10 will be described indetail with reference to a timing chart of FIG. 11. The timing chart ofFIG. 11 shows one field (1 f) starting in timing T1 and ending in timingT6. The waveforms of a pulse ws applied to the scanning line WS, a pulsex applied to the scanning line X, and a pulse y applied to the scanningline Y are shown along a time axis T. In addition, changes in potentialsof the input node A, the intermediate node C, and the output node B areshown along the same time axis T. The change in the potential of theinput node A and the change in the potential of the output node B arerepresented by a solid line, and the change in the potential of theintermediate node C is represented by a dotted line to be distinguishedfrom the change in the potential of the input node A and the change inthe potential of the output node B.

In timing T0, before entering the field, the scanning lines WS and X aremaintained at a low level while the scanning line Y is at a high level.Therefore, the sampling transistor Tr1 and the switching transistorsTr3, Tr4, Tr6, and Tr7 are off, and only the switching transistors Tr5and Tr8 are in an on state. At this time, as shown in the timing chart,there is a potential difference substantially equal to an inputpotential Vin between the potential of the input node A and thepotential of the output node B; therefore, the drive transistor Tr2 isin an on state to supply a driving current (drain current) Ids to thelight emitting element EL.

When entering the field, the scanning line Y is changed to a low levelin timing T1. Thereby the switching transistors Tr5 and Tr8 are turnedoff. Therefore, the light emitting element EL is disconnected from theoutput node B and thus goes into a non-emitting state. The switchingtransistors Tr3 and Tr4 are also in an off state in timing T1 inaddition to the switching transistor Tr5. Therefore, the terminal node Dof the retaining capacitance C1 has a high impedance. The operation intiming T1 corresponds to a preparation for sampling an input signal inthe field.

In timing T2, a selection pulse ws is applied to the scanning line WSand a selection pulse x is applied to the scanning line X. The scanningline WS is thereby changed to a high level to turn on the samplingtransistor Tr1 and the switching transistor Tr3. At the same time, thescanning line X is changed from a low level to a high level so that thetransistors Tr4, Tr6, and Tr7 are turned on.

Since the switching transistor Tr3 is turned on, the terminal node D isconnected to the ground potential Vss. Since the switching transistorTr4 is turned on, the output node B is directly connected to theterminal node D. As a result, the potential of the output node B issharply decreased to the ground level Vss. At this time, since thesampling transistor Tr1 is also turned on, an input signal Vsig suppliedto the signal line DL is written to the retaining capacitance C1. Themagnitude of a written signal potential Vin is substantially equal tothat of the voltage of the input signal Vsig. Since the terminal node Dis fixed at the ground potential Vss, the potential of the input node Ais precisely Vin as shown in the timing chart. This input potential Vinis applied between the gate G and the source S of the drive transistorTr2 so that a drain current Ids, corresponding to the signal potentialVin, flows out from the output node B.

However, since the switching transistor Tr8 is in an off state asdescribed above, the drain current Ids is not supplied to the lightemitting element EL. The light emitting element EL, therefore, continuesmaintaining the non-emitting state.

When one horizontal period (1H), assigned to the operation of writing ofthe input signal, has passed the selection pulse ws is cleared in timingT3 to return the scanning line WS from a high level to a low level.Thereby the sampling transistor Tr1 and the switching transistor Tr3 areturned off. As a result, the terminal node D and the output node B aredisconnected from the ground potential Vss. In response to this, thepotential of the output node B starts to rise, and the drain current Idsstarts to flow into the detecting capacitance C3 via the switchingtransistor Tr7 in an on state. With accumulation of charge, thepotential of the output node B continues rising. At this time, since theterminal node D is disconnected from the ground potential Vss, thepotential of the input node A rises in such a manner as to beinterlocked with the potential of the output node B. A potentialdifference Vin between the input node A and the output node B is keptconstant.

In timing T4, after the passage of a predetermined time t from timingT3, the selection pulse x is cleared to return the scanning line X froma high level to a low level. The transistors Tr4, Tr7 and Tr6 arethereby turned off. In a stage in which the switching transistor Tr7 isturned off, the charge accumulation of the detecting capacitance C3 iscompleted. The potential of the detecting capacitance C3 which potentialcorresponds to the accumulated charge is given by

VC3=(Ids/C3)·t. As is clear from this equation, the detection potential

VC3 is proportional to the drain current Ids because the capacitancevalue C3 and the accumulation time t are fixed. That is, the detectionpotential

VC3 has a value proportional to the drain current Ids of the drivetransistor Tr2. As the mobility μ of the drive transistor Tr2 isdecreased with the passage of time, the detection potential

VC3 is correspondingly lowered.

The switching transistors Tr6 and Tr7 are in an on state untilimmediately before the scanning line X falls to a low level in timingT4. The feedback capacitance C2 is therefore at the potential Vin of theinput signal Vsig on the side of the intermediate node C. The potentialof the feedback capacitance C2 on the side of the output node B isprecisely

VC3. Hence, when the selection pulse x is cleared and the switchingtransistors Tr6 and Tr7 are thereby turned off, the feedback capacitanceC2 holds a potential

Vμ corresponding to a difference between the potential Vin and thedetection potential

VC3. That is, the potential

Vμ is expressed by

Vμ=Vin−

VC3. As described above, when the drain current Ids is decreased, due todegradation of the drive transistor Tr2, the detection potential

VC3 is also decreased. Hence, the potential

Vμ is increased. By feeding back the potential

Vμ, held by the feedback capacitance C2 to the side of the input node A,it is possible to cancel the decrease in the drain current Ids. Thisfeedback operation makes it possible to continue supplying the draincurrent Ids having the same level as an initial level even when adegradation occurs in an operation characteristic of the drivetransistor Tr2 such as mobility or the like.

The comparison example compares and determines the magnitude of thedetection potential

VC3 with the signal potential Vin of the input signal Vsig as areference. The signal potential Vin varies in a predetermined range (forexample 0 to 5 V). The drain current Ids correspondingly varies, and thedetection potential

VC3 has a corresponding level. The signal potential Vin and thedetection potential

VC3 thus change in the same direction so that dynamic comparison ispossible. As a precondition, the dynamic range of the signal potentialVin and the dynamic range of the detection potential

VC3 need to substantially match each other. Supposing that the dynamicrange of the signal potential Vin is 0 to 5 V as described above, it isdesirable that the detection potential

VC3 vary in substantially a range of 0 to 5 V. In order to set thedynamic range of the detection potential

VC3 to the desired range, it is necessary to set the accumulation time tand the capacitance of the detecting capacitance C3 appropriately.

Thereafter, in timing T5, a selection pulse y is applied to change thescanning line Y from a low level to a high level. The switchingtransistors Tr5 and Tr8 are thereby turned on. By turning on theswitching transistor Tr8, the anode of the electrooptic element EL isdirectly connected to the output node B. By turning on the switchingtransistor Tr5, the intermediate node C is directly connected to theterminal node D. The difference

Vμ, retained by the detecting capacitance C2, as well as the signalpotential Vin, retained by the retaining capacitance C1, is appliedbetween the input node A and the output node B. The drive transistor Tr2supplies a drain current Ids corresponding to Vin+

Vμ to the light emitting element EL, whereby light emission is started.Due to a voltage drop occurring in the light emitting element EL, thepotential of the output node B is increased. The potential of the inputnode A is also increased in such a manner as to be interlocked with thepotential of the output node B. This bootstrap operation maintains apotential difference between the input node A and the output node B atthe value of Vin+

Vμ. As described above, when the drain current Ids is decreased, due todegradation of the drive transistor Tr2, the difference

Vμ is increased so as to compensate for the decrease. This feedbackoperation suppresses the variation in the drain current Ids so that thedrain current Ids, having the same level as an initial level, can bemade to flow irrespective of change in the mobility μ of the drivetransistor Tr2.

Thereafter, in timing T6, the scanning line Y falls to a low level toturn off the switching transistor Tr8, whereby the light emission isended. Thereby a series of operations in the field is completed, and anext field is started.

FIG. 14 is a schematic circuit diagram showing another embodiment of apixel circuit according to the present invention. In order to facilitateunderstanding, corresponding reference numerals are used as much aspossible to denote parts corresponding to those of the pixel circuitaccording to the reference example shown in FIG. 6. As shown in thefigure, this pixel circuit 5 is disposed at a part where a scanning lineand a signal line intersect each other. A signal line DL is a singleline, while four scanning lines WS, X, Y, and Z are bundled together andarranged in parallel with each other. The pixel circuit 5 includes alight emitting element EL, a drive transistor Tr2, a sampling transistorTr1, and a retaining capacitance Cs as fundamental components. The drivetransistor Tr2 has a gate G connected to an input node A, a source Sconnected to an output node B, and a drain connected to a predeterminedpower supply potential Vcc. The light emitting element EL is, forexample, a diode type, two-terminal element such as an organic ELelement or the like. The light emitting element EL has an anode, as oneterminal connected to the output node B, and a cathode, as anotherterminal connected to a predetermined potential Vcath. The samplingtransistor Tr1 is connected between the input node A and the signal lineDL. The gate of the sampling transistor Tr1 is connected to the scanningline WS. The retaining capacitance Cs is connected to the input node A.In such a configuration, the sampling transistor Tr1 operates whenselected by the scanning line WS, samples an input signal Vsig from thesignal line DL, and retains the input signal Vsig in the retainingcapacitance Cs. The drive transistor Tr2 supplies a driving current tothe light emitting element EL according to the signal potential retainedin the retaining capacitance Cs. In the example shown in the figure, thedrive transistor Tr2 outputs a drain current Ids from the output node B,and supplies the drain current Ids as the driving current to the lightemitting element EL. The light emitting element EL emits light with avoltage drop occurring according to the driving current Ids.

As a feature of the present invention, the pixel circuit 5 incorporatesa compensating circuit 7 for compensating for a decrease in brightnessdue to a secular change of the light emitting element EL. Thiscompensating circuit 7 detects the voltage drop increasing according tothe secular change of the light emitting element EL from the side of theoutput node B, and feeds back a signal potential corresponding to thelevel of the detected voltage drop to the side of the input node A. Thedrive transistor Tr2 supplies the sufficient drain current Ids tocompensate for a decrease in brightness of the light emitting element ELaccording to the fed-back signal potential. Thus, the present inventiondirects attention to a tendency for the voltage drop to increase as thebrightness is degraded as a general tendency of the light emittingelement and compensates for a decrease in the brightness of the lightemitting element with the passage of time utilizing this tendency. Thatis, as the brightness is degraded, the voltage drop within the lightemitting element EL increases. This voltage drop is detected and fedback to the side of the input node as a signal potential, whereby thedegradation in the brightness is made up for. That is, as the brightnessis degraded, the voltage drop increases. This voltage drop is fed backto the drive transistor, whereby the driving current is increased. Thisincrease in the driving current always acts in a direction to make upfor degradation in the brightness.

As for a concrete configuration, the compensating circuit 7 includes twodetecting capacitances C1 and C2 and five switching transistors Tr3 toTr7. The two detecting capacitances C1 and C2 are connected in serieswith each other between the output node B and the input node A. In thefigure, a point of interconnection between the two detectingcapacitances C1 and C2 is indicated by an intermediate node C. The twodetecting capacitances C1 and C2, connected in series with each other,detect the voltage drop occurring in the light emitting element EL fromthe side of the output node B, and each retain the voltage dropaccording to a capacitance dividing ratio. Also, the level of an amountof the voltage drop, which amount is retained by the detectingcapacitance C2, situated on the side of the input node A, is fed back asa signal potential to the side of the input node A.

The five switching transistors Tr3 to Tr7 are arranged to operate thetwo detecting capacitances C1 and C2 in the above-described sequence.The switching transistors Tr3 to Tr7 are controlled to be turned on/offby corresponding scanning lines. Specifically, the switching transistorTr5 is inserted in parallel with one of the two detecting capacitancesC1 and C2 connected in series with each other that is situated on theside of the output node B, that is, the detecting capacitance C1. Inother words, the switching transistor Tr5 is connected between theoutput node B and the intermediate node C. The gate of the switchingtransistor Tr5 is connected to the scanning line Y. The switchingtransistor Tr7 is inserted between the other detecting capacitance C2,situated on the side of the input node A, and a predetermined groundpotential Vss. The gate of the switching transistor Tr7 is connected tothe scanning line X. The switching transistor Tr6 is inserted betweenthe other detecting capacitance C2, situated on the side of the inputnode A, and the input node A. The gate of the switching transistor Tr6is connected to the scanning line Y. The switching transistor Tr3 isinserted between the retaining capacitance Cs and the predeterminedground potential Vss. The gate of the switching transistor Tr3 isconnected to the scanning line Z. The other switching transistor Tr4 isinserted between the retaining capacitance Cs and the output node B. Thegate of the switching transistor Tr4 is connected to the scanning lineX.

The operation of the pixel circuit shown in FIG. 14 will be described indetail with reference to a timing chart of FIG. 15. The timing chart ofFIG. 15 shows one field (1 f) starting in timing T1 and ending in timingT6. The waveforms of a pulse ws, applied to the scanning line WS, apulse x, applied to the scanning line X, a pulse y, applied to thescanning line Y, and a pulse z, applied to the scanning line Z, areshown along a time axis T. In addition, changes in potentials of theinput node A, the intermediate node C, and the output node B are shownalong the same time axis T. The change in the potential of the inputnode A and the change in the potential of the intermediate node C arerepresented by a solid line, and the change in the potential of theoutput node B is represented by a chain line to be distinguished fromthe change in the potential of the input node A and the change in thepotential of the intermediate node C. In timing T0, before entering thefield, the scanning lines WS, Z, and X are at a low level, while thescanning line Y is at a high level. Therefore, the sampling transistorTr1 and the switching transistors Tr3, Tr4, and Tr7 are off, while theswitching transistors Tr5 and Tr6 are in an on state.

Entering the field in question from the above-described state in aprevious field, the scanning lines Z and X rise from a low level to ahigh level in timing T1. Thereby the switching transistors Tr3, Tr4, andTr7 are turned on. Therefore, the switching transistors Tr3 to Tr7,included in the pixel circuit 5, are all turned on. Hence, the terminalsof the retaining capacitance Cs and the detecting capacitances C1 and C2are all short-circuited, and thus all of charge stored in the previousfield is discharged. Therefore, in timing T1, the charge of theretaining capacitance Cs and the detecting capacitances C1 and C2 arecleared, and thus the retaining capacitance Cs and the detectingcapacitances C1 and C2 are reset to be ready for new operation in thefield in question.

Since all the switching transistors Tr3 to Tr7 conduct, the input nodeA, the output node B, and the intermediate node C are decreased to theground potential Vss. A potential difference between the input node Aand the output node B becomes zero. Thus, the drain current Ids does notflow through the drive transistor Tr2 so that the light emitting elementEL is put in a non-emitting state.

In timing T1′, after the passage of a short time from timing T1, thescanning line Y is changed from a high level to a low level, and theswitching transistors Tr5 and Tr6 are thereby turned off. Therefore, thedetecting capacitances C1 and C2, connected in series with each, otherare disconnected from the side of the input node A to be put in astandby state for voltage drop detection to be performed later.

In timing T2, a selection pulse ws is applied to the scanning line WS,and the sampling transistor Tr1 is thereby turned on. Thus, an inputsignal Vsig, supplied from the signal line DL, is sampled into theretaining capacitance Cs, and a signal potential Vin is retained in theretaining capacitance Cs. That is, the potential of the input node Abecomes precisely the signal potential Vin with the ground potential Vssas a reference. The signal potential Vin is applied between the inputnode A and the output node B; accordingly, the drive transistor Tr2starts to pass the drain current Ids.

When one horizontal period (1H), assigned to the sampling of the inputsignal Vsig, has passed the selection pulse ws is cleared in timing T3to return the sampling transistor Tr1 to an off state. At the same time,the scanning line Z is changed from a high level to a low level to turnoff the switching transistor Tr3 so that the retaining capacitance Csand the output node B are disconnected from the ground potential Vss.The drain current Ids, supplied from the drive transistor Tr2, flowsinto the light emitting element EL; accordingly, a voltage drop

Vel occurs. The potential of the output node B rises by the amount ofthis voltage drop

Vel with respect to the ground potential Vss. At this time, since theretaining capacitance Cs is disconnected from the ground potential Vss,the potential of the input node A is also raised in such a manner as tobe interlocked with the potential of the output node B by bootstrapoperation. At this time, the potential difference Vin between the inputnode A and the output node B is maintained at a constant value by thebootstrap operation.

In timing T3, the switching transistor Tr5 is in an off state, while theswitching transistor Tr7 is in an on state. Therefore, the pair ofdetecting capacitances C1 and C2 is connected in series with each otherbetween the output node B and the ground potential Vss. The draincurrent Ids, supplied from the output node B, also flows into thedetecting capacitances C1 and C2, connected in series with each other,and the voltage drop

Vel, appearing at the output node B, is precisely retained by the twodetecting capacitances C1 and C2, according to the capacitance dividingratio between the detecting capacitances C1 and C2. A voltage dropcomponent

V, retained in the detecting capacitance C2, is

V=

Vel×C1/(C1+C2), according to the capacitance dividing ratio. Thisvoltage drop component

V appears precisely as the potential of the intermediate node C, withrespect to the ground potential Vss in the timing chart of FIG. 15.Thus, by capacitive coupling, the detecting capacitance C2 retains thesignal potential

V according to the voltage drop

Vel of the light emitting element EL.

Next, in timing T4, the scanning line X is returned to a low level,whereby the switching transistors Tr4 and Tr7 are turned off. As aresult, the retaining capacitance Cs is disconnected from the outputnode B, and the detecting capacitance C2 is disconnected from the groundpotential Vss.

Further, in timing T5, the scanning line Y is changed from a low levelto a high level, whereby the switching transistors Tr5 and Tr6 areturned on. Thus, the detecting capacitance C2 is directly connectedbetween the output node B and the input node A. The signal potential

V, retained in the detecting capacitance C2, is, therefore, appliedbetween the input node A and the output node B. The drive transistor Tr2supplies a drain current Ids to the light emitting element EL accordingto the signal potential

V. The light emitting element EL is thereby brought into a lightemitting state to display an image. As shown in the timing chart of FIG.15, the signal voltage

V applied after timing T5 is represented as

Vel×C1/(C1+C2). As described above, as the brightness of the lightemitting element EL is decreased with the passage of time, the voltagedrop

Vel is increased. The signal voltage

V is proportional to the voltage drop

Vel with a proportionality constant C1/(C1+C2). This signal voltage

V is fed back to the side of the input node A. Thus, as the voltage drop

Vel is increased, the drain current Ids is increased to compensate forthe decrease in the brightness of the light emitting element EL.

Thereafter, in timing T6, the scanning lines Z and X are returned to ahigh level, whereby all the switching transistors Tr3 to Tr7 are turnedon to perform a reset operation in preparation for a next frame.

It should be understood by those skilled in the art that variousmodifications, combinations, sub-combinations and alterations may occurdepending on design requirements and other factors insofar as they arewithin the scope of the appended claims or the equivalents thereof.

1-20. (canceled)
 21. A display device comprising pixel circuits arranged in a form of a matrix; a given one of the pixel circuits including: an electro-optical element, a drive transistor, a storing capacitance, and a correction circuit; wherein the drive transistor and the electro-optical element are arranged in a series connection to form a current path between a power supply line and a ground line, the drive transistor is configured to control a driving current through the current path according to an image signal provided via a signal line; the correction circuit includes a first transistor and a second transistor, and is configured to provide, in a predetermined period before a light emission period, a current through the first transistor to the storing capacitance, the first transistor is connected to the drive transistor, and the second transistor is put in a cut-off state during the predetermined period and is put in a conductive state in the light emission period, such that the correction circuit sets a voltage between a gate node and a current node of the drive transistor during the light emission period to a value depending on both of a characteristic data of the drive transistor and the image signal.
 22. The display device as claimed in claim 21, wherein the correction circuit is configured to set to a voltage of the storing capacitance to a value dependent on a charge amount carried by the driving transistor in the predetermined period.
 23. The display device as claimed in claim 22, wherein the correction circuit includes a first capacitor connected to the current path, the first capacitor being configured to store a voltage dependent on the charge amount.
 24. The display device as claimed in claim 23, wherein the first capacitor is connected between the gate node and the current node of the drive transistor, so that, in the light emission period, the voltage between the gate node and the current node of the drive transistor includes a signal stored in the first capacitor.
 25. The display device as claimed in claim 24, wherein the second transistor and the first capacitor are connected in series between the gate nodes and the current node of the drive transistor.
 26. The display device as claimed in claim 25, wherein the correction circuit further includes a second capacitor configured to store a voltage dependent on the image signal, and the second capacitor, the second transistor and the first capacitor are connected in series between the gate node and the current node of the drive transistor, so that, in the light emission period, the voltage between the gate node and the current node of the drive transistor is defined by a total of voltages stored in the first capacitor and the second capacitor.
 27. The display device as claimed in claim 21, wherein during the predetermined period, the storing capacitance is electrically connected to a signal line via a transistor whose gate node is connected to a same control line as a control line connected to the first transistor.
 28. The display device as claimed in claim 21, wherein the drive transistor and the electro-optical element are directly connected without any intervening transistors.
 29. The display device as claimed in claim 28, wherein the pixel circuit is configured to have a tentative emission period before the light emission period, and the correction circuit detects a current through the current path during the tentative emission period.
 30. The display device as claimed in claim 29, wherein the tentative emission period corresponds to the predetermined period.
 31. The display device as claimed in claim 21, wherein the electro-optical element is an organic EL element.
 32. The display device as claimed in claim 21, wherein the given one of the pixel circuits further includes a sampling transistor connected to the signal line and configured to sample the image signal from the signal line.
 33. The display device as claimed in claim 21, wherein the correction circuit further includes a third transistor connected between the storing capacitance and a potential line which is different from the signal line.
 34. The display device as claimed in claim 33, wherein the third transistor is configured to be put in a conductive state before the predetermined period so as to provide a predetermined potential to the storing capacitance.
 35. The display device as claimed in claim 34, wherein the predetermined potential is not higher than the lowest voltage within a range corresponding to the image signal.
 36. The display device as claimed in claim 34, wherein the given one of the pixel circuits further includes a sampling transistor connected to the signal line, and configured to sample the image signal from the signal line while the third transistor is put in a conductive state before the predetermined period.
 37. The display device as claimed in claim 33, wherein the correction circuit is configured to electrically connect an anode of the electro-optical element to the potential line.
 38. The display device as claimed in claim 37, wherein the predetermined potential is not higher than the lowest voltage within a range corresponding to the image signal.
 39. The display device as claimed in claim 33, wherein the first transistor, third transistor and the storing capacitance are connected together at a common node.
 40. The display device as claimed in claim 21, wherein the correction circuit is configured to electrically connect an anode of the electro-optical element to a potential line. 